T8531A-TL-DT Agere Systems, Inc., T8531A-TL-DT Datasheet
T8531A-TL-DT
Related parts for T8531A-TL-DT
T8531A-TL-DT Summary of contents
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... Available in 64-pin MQFP and TQFP packages General Description The multichannel programmable codec chip set is comprised of the T8531A 16-channel line card signal processor and one or two custom T8532 octal A/D and D/A converters. A ROM-coded tone plant, with line-test and self-test utilities, is included on the sig- nal processor ...
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... Interchip Control Interface ................................... 14 T8531A Functional Blocks ..................................... 14 Clock Synthesizer................................................ 14 T8531A System Interface ................................... 15 T8531A Microprocessor Interface ....................... 15 T8532 Octal Control Interface ............................. 16 T8531A Time-Slot Assignment (TSA) ................. 16 DSP Engine Timing................................................ 16 T8531A Program Structure ................................. 16 Control of the DSP Engine via the Microprocessor Interface .................................. 17 The DSP Engine Time-Slot Information Tables ...
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... Table 32. T8531A Control Register Map ...................39 Table 33. Bits 15:8 of T8531A Board Control Word 1 at 0x1FFE ..................................................40 Table 34. Bits 7:0 of T8531A Board Control Word 1 at 0x1FFE ..................................................40 Table 35. Bits 15:9 of T8531A Board Control Word 2 at 0x1FFC..................................................41 Table 36. Bits 8:0 of T8531A Board Control Word 2 at 0x1FFC..................................................41 Table 37. Bits 15:0 of T8531A Board Control Word 3 at 0x1FFA ...
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... A/D and D/A converters, reconstruction and smoothing filters, termination impedance synthesis, and selectable gain. The digital oversampled data is multiplexed onto a serial data port designed to interface with the T8531A Another serial interface accepts control data from the T8531A for activating the various gain settings, self-test, and powerdown modes ...
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... T8531A Description As shown in Figure 4, the T8531A contains a digital signal processor (DSP) engine surrounded by a customized input/output (I/O) frame. The I/O frame performs the -law or A-law conversion as well as the decimation and inter- polation functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The sigma-delta converters operate ...
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... Figure 6. Control, PCM, and Octal Interfaces 6 REL REL ABS ABS RDG RDG RDG RDG BALANCE BALANCE FILTER FILTER REL TDG Figure 5. T8531A Digital ac Path OCTAL INTERFACE T8531A 8 kHz SYNC OSFS UPCK 4 MHz CLOCK OSCK UPCS DATA OSDR0 UPDI OSDR1 DATA UPDO ...
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September 2001 Pin Information 64 63 VRTX7 1 VRP7 2 VRN7 SSA VRN6 5 VRP6 6 VRTX6 7 VTX6 DDA VTX5 10 VRTX5 11 VRP5 12 VRN5 SSA VRN4 15 VRP4 ...
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... T8531A through each of these pins. The data rate is 4.096 MHz. Oversampled Receive Data. Four channels of 1.024 MHz - receive data is received from the T8531A on each of these pins. The data rate is 4.096 MHz. Interface Clock. The 4.096 MHz clock that enters this pin from the T8531A serves as the bit clock for all the oversampled data transmission between this chip and the T8531A This is the master clock input for the T8532 ...
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... SSA Agere Systems Inc T8531A Figure 8. T8531A 64-Pin TQFP Codec Chip Set JTESTB OSDX2 44 OSDR2 43 OSDX3 42 OSDR3 OSFS 39 OSCK ...
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... MHz SCK. An internal pull-up device is included, pro- viding 4.096 MHz SCK operation with no external connections. Receive PCM Input. The data on this pin is shifted into the T8531A on the falling edges of SCK. Data is only entered for valid time slots as defined in the TSA registers ...
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... September 2001 Pin Information (continued) Table 2. T8531A Pin Descriptions (continued) Number Name 23 SDX 21 SFS 54 CDO 51 CDI 53, 52 CCS[1:0] 7 TCK 4 TDI 5 TDO 6 TMS 48 JTESTB 59 HIGHZB 60 TEST 61 CK16 8 TSTCLK 1, 12, 14 T_SYNC 58 RSTB 3, 10, 16, 19 25, 31, 34, 46, 50, 56 15, 18, 26, ...
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... The signal level to produce a 0 dBm0 level at the digital transmit output of the T8531A is not a fixed quantity as explained above. For a line with a complex impedance echo signal, extra headroom must be allowed and the TX signal level must be set to account for the headroom ...
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... Hybrid Balance The hybrid balance function is provided as a digital block in the T8531A The T8531A implements a 9-tap FIR and a single-pole IIR digital balance filter in which a replica of the echo is digitally subtracted from the transmit plus near-end echo signal. The coefficients are user programmable on a per-line basis via the microprocessor interface ...
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... Unlike the ACT register, this digital loopback mode is selectable per channel. This loop- back mode can be used to check T8532 functionality from the T8531A device also used during the cali- bration sequence. There is one loopback mode in the T8531A Loopback at the oversampled data interface is controlled by board control word 1 ...
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... Address and data are 16 bits wide. The T8531A expects an address first. The first bit of the address word is the R/W flag, which tells the T8531A whether it must receive or send data (receive, R send 1). Addresses less than 0x1400 refer to the DSP engine RAM space ...
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... The data rate of 2.048 MHz allows 256 SCK cycles in a frame, i.e., eight address/data pairs with no pause between words. Since the DSP engine can process only one interrupt every 7.8 s, the T8531A requires a separation between address and data on read and write instructions to the microprocessor interrupt (see Figure 10) ...
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September 2001 Chip Set Functional Description (continued) DSP Engine Timing (continued) Control of the DSP Engine via the Microprocessor Interface There are four types of commands that the external controlling device may issue to the DSP engine: 1. Downloading data ...
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... Operations Performed by the DSP Engine at T8531A Start-Up The DSP engine performs its start-up code after it has been reset. All interrupts are disabled. First, the DSP engine computes the checksum for its ROM and RAM to verify their integrity. Next, the DSP engine walks through each time-slot information table and sets the data buffer and coefficient pointers ...
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September 2001 Chip Set Functional Description (continued) DSP Engine Timing (continued) Microprocessor Start-Up of the DSP Engine Once the interrupt system is enabled, the DSP engine looks for a read or write interrupt from the microproces- sor interface once every ...
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... The DSP engine firmware is ROM based. The hard- ware development system code is also ROM based. The DSP engine ROM memory map is given in Table 41. Table 7. Summary of Microprocessor Commands for Control of T8531A Data Processing Function Required Bulk TSA register download & BCW2 Individual TSA register download ...
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... SCKSEL pin. 2. The T8531A custom logic jams all resettable latches, counters, and registers to their default val- ues. No data is latched on any of the T8531A inter- faces during internal reset. 3. The DSP engine is held in reset state. 4. The internal reset line is held low for a minimum allow the frequency synthesizer to reach its final accuracy ...
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... T8531A/T8532 User Manual and the T8531A ROM Routines User Manual . Off-Line Programmable System Test Capability The T8531A has a standard 4-pin test access port known as JTAG that can be used for testing and debugging. The user has the option of downloading ...
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... Agere Systems Inc. Tone Plant The following tone plant functions are provided in ROM code in the T8531A device. Refer to the T8531 and T8531A Tone Processing manual for more information DTMF Transceiver DTMF generation and detection satisfies LSSGR Sig- naling for Analog Interfaces GR-506 CORE, section 15 ...
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Codec Chip Set Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any ...
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September 2001 Electrical Characteristics For all specifications – + and Input signal frequency is 1020 Hz, unless otherwise noted. DSP clock frequency ...
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... Absolute GAL Levels (T8532 TX gain = 0 dB; T8531A gain = –1.65 dB) (T8532 RX gain = 6.02 dB; T8531A gain = 0.21 dB) (T8532 TX gain =12.04 dB; T8531A gain = –1.65 dB) (T8532 RX gain = –12.04 dB; T8531A gain = 0.21 dB) Transmit Gain GXA Absolute 0 dBm0 test level, measured deviation of digital code Accuracy from ideal 0 dBm0 level at OSDX[1:0] digital outputs, ...
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September 2001 Transmission Characteristics Table 12. Gain and Dynamic Range (continued) Parameter Symbol Transmit Gain Variation GXAF with Frequency Transmit Gain Variation GXAL with Signal Level Receive Gain Absolute GRA Accuracy Relative Gain: — VRP to VRN Relative Phase: — ...
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Codec Chip Set Transmission Characteristics Table 13. Noise (per Channel) Parameter Symbol Transmit Noise C-message Weighted Transmit Noise P-message Weighted Receive Noise C-message Weighted Receive Noise P-message Weighted Noise, Single Frequency N ...
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September 2001 Transmission Characteristics Table 14. Distortion and Group Delay Parameter Symbol Signal to Total Distortion Transmit or Receive C-message Weighted Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion TX Group Delay, Absolute RX Group Delay, Absolute * ...
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Codec Chip Set Timing Characteristics A signal is valid above V or below V IH fication, the following conditions apply: All input signals are defined measured from ...
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September 2001 Timing Characteristics (continued) TIME SLOT tFSHFSL SFS tSFHSCL tSCLSFL SCK tSCHDXV * SDX † SDR Card address 0, bit offset 0 assumed. † Card ...
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Codec Chip Set Timing Characteristics (continued) Table 17. Serial Control Port Timing (See Figure 10.) Symbol Parameter tCSHLSET UPCS to UPCK Setup tCSLHHOD UPCS to UPCK Hold tUPDIST UPDI to UPCK Setup tUPDIHD UPDI to UPCK Hold tUPDODEL UPCK to ...
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... September 2001 Software Interface Table 18 lists the RAM data space for the DSP engine. Space for channels is allocated. The total T8531A RAM size is 4 Kwords, arranged Kbanks. Address bit 15 is used as a read/write flag (1 = read). The micro- processor interface can read any address in the DSP engine RAM space. ...
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Codec Chip Set Software Interface (continued) Table 18. DSP Engine RAM Memory Map (continued) Address Range 0x04B5 Channel 8 ac filter coefficients 0x04C5 Channel 9 ac filter coefficients 0x04D5 Channel 10 ac filter coefficients 0x04E5 Channel 11 ac filter coefficients ...
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... Table 20A. Bit Map for T8531A Time-Slot Assignment Registers at 0x1400—0x140F 15—6 5 Not used CTZ disable Null channel Table 20B. Bit Map for CTZ Disable and Null Channel Bit 5 Bit ...
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... Channel 4 control register 2 0x151D Channel 5 control register 2 0x151E Channel 6 control register 2 0x151F Channel 7 control register 2 36 Table 22. T8531A Channel Register Memory Map for T8532 Device 1 All registers can be written by the microprocessor interface. Address Memory Range Contents 0x1540 Channel 8 powerup/powerdown register ...
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September 2001 Software Interface (continued) Table 23. Bit Map for T8532 Powerup/Powerdown Registers at 0x1500—0x1507 and 0x1540—0x1547 15 PWR Notes: PWR = 0: powerdown. PWR = 1: powerup—normal operation. Table 24. Bit Map for T8532 Channel Control Register 1 at ...
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Codec Chip Set Software Interface (continued) Table 27. T8532 Control Register 1: Digital Loopback Bit 0 LPBK 0 1 Table 28. Bit Map for T8532 All Channel Test Register at 0x1510 and 0x1550 15—4 Not used Read out address Table ...
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... Table 32. T8531A Control Register Map Address Range 0x1FFE 0x1FFC 0x1FFA 0x1FF8 0x1FF6 Note: A board control word controls a function that is common to all 16 channels of a given chip set. Agere Systems Inc. Bit Number and Function 6—3 2 Not used ...
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... Table 34. Bits 7:0 of T8531A Board Control Word 1 at 0x1FFE Bit Number — — — — — — — — ...
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... Table 38. Bits 15:0 of T8531A Board Control Word 4 at 0x1FF8 Bit Number and Function 15—10 Not used Note: The default value after hardware reset or powerup is A4. Table 39. Bits 15:0 of T8531A Board Control Word 5 at 0x1FF6 Bit Number and Function 15—8 Not used Note: The default value after hardware reset or powerup is 0. ...
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Codec Chip Set Software Interface (continued) Table 41 shows the memory map for the DSP engine ROM. The ROM information is not accessible via the micro- processor. The total ROM size is 8 Kwords. Table 41. DSP Engine ROM Memory ...
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September 2001 Software Interface (continued) Table 41. DSP Engine ROM Memory Map Address Range 0x0FFF Checksum for ROM 0x0800 : 0x0FFD 0x1000 Call progress tone generation start 0x102B Call progress tone generation during operation 0x105A Call progress tone generator initialization ...
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... The analog connection between the SLIC and the codec is direct; no external components are required. The trans- fer of control data on the octal interface between the T8531A and T8532 devices is also direct. Data is synchro- nous with OSCK and transmits at a 4.096 MHz rate. The microprocessor control interface is a standard 4-wire serial port connection, microprocessor clock (UPCK), chip select (UPCS), data input (UPDI), and output (UPDO) ...
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September 2001 Applications (continued) Figure 12 shows the complete SLIC schematic for interfacing to the Agere L9215G short-loop, sine wave, ringing SLIC. All ac parameters are programmed by the codec. Note, this codec differentiates itself in that no external components ...
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Codec Chip Set Applications (continued) Figure 13 shows the complete SLIC schematic for interfacing to the Agere L9310G Line Interface and Line Access circuit. All ac parameters are programmed by the codec. Note, this codec differentiates itself in that no ...
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... VTX inputs. VREFx Agere Systems Inc – 1.91 k 0.1 F 1/2 LM2904 RL OR EQUIVALENT Figure 14. Common 2.4 V Voltage Reference Codec Chip Set VRTX15 VRTX1 VRTX0 R VREF0 TO VTX0 301 k T8531A VREF1 10 F VTX1 301 k R VREF15 VTX15 301 k 12-3570a (F) 47 ...
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Codec Chip Set Outline Diagrams 64-Pin MQFP 1 16 DETAIL A 1.60 REF GAGE PLANE SEATING PLANE 48 17.20 0.25 14.00 0.20 PIN #1 IDENTIFIER ZONE DETAIL B 2.55/2.75 0.80 TYP 0.25 MAX 0.25 0.30/0.45 0.73/1.03 ...
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September 2001 Outline Diagrams (continued) 64-Pin TQFP DETAIL A 0.50 TYP 0.19/0.27 DETAIL B Agere Systems Inc. 12.00 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE 49 48 10.00 0. DETAIL B 1.40 0.05 1.60 ...
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Codec Chip Set Ordering Information Device Code T-8531A - - - TL-DB 64-Pin TQFP, Dry pack tray T-8531A - - - TL-DT 64-Pin TQFP, Dry-bagged, Tape & Reel T-8532 - - - JL-DB 64-Pin MQFP, Dry pack tray T-8532 - ...