CD2401 Intel, CD2401 Datasheet
CD2401
Related parts for CD2401
CD2401 Summary of contents
Page 1
... The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer schemes. Each channel and direction in the dual-buffer scheme has two active buffers. The CD2401 can be programmed to interrupt the host at the completion of a frame or buffer. In applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames to be divided into multiple buffers ...
Page 2
... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The CD2401 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
Page 3
... Groups and Types..................................................................................39 5.2.4 Hardware Signals and IACK Cycles .......................................................41 5.2.5 Multi–CD2401 Systems..........................................................................42 5.3 FIFO and Timer Operations ................................................................................43 5.3.1 Receive FIFO Operation ........................................................................43 5.3.2 Transmit FIFO Operation .......................................................................43 5.3.3 Timers ....................................................................................................43 5.3.4 Timers in Synchronous Protocols...........................................................44 5.3.5 Timers in Asynchronous Protocols.........................................................44 5.3.6 Transmit Timer .......................................................................................44 5.4 DMA Operation....................................................................................................44 5.4.1 Bus Acquisition Cycle.............................................................................45 Datasheet Multi-Protocol Communications Controller — CD2401 ..........................................................................................................15 ............................................................................................................21 ...........................................................................................35 3 ...
Page 4
... Transmit DMA Transfer .......................................................................... 48 5.4.6 Synchronous Transmitter Examples ...................................................... 49 5.4.7 Receive DMA Transfer ........................................................................... 51 5.5 Bit Rate Generation and Data Encoding ............................................................. 58 5.6 Hardware Configurations .................................................................................... 65 5.6.1 Interface to a 32-Bit Data Bus ................................................................ 66 5.6.2 CD2401 as a DTE and DCE Interface.................................................... 67 6.0 Protocol Processing 6.1 HDLC Processing................................................................................................ 68 6.1.1 Frame Check Sequence ........................................................................ 68 6.1.2 HDLC Transmit Mode............................................................................. 68 6.1.3 HDLC Receive Mode ............................................................................. 69 6.2 Async Processing ...
Page 5
... General Timer 1 (GT1) Register – Sync Modes only ...........................154 8.7.4 General Timer 2 (GT2) Register — Sync Modes only..........................155 8.7.5 Transmit Timer Register (TTR) — Async Modes only..........................156 9.0 Electrical Specifications 9.1 Absolute Maximum Ratings...............................................................................157 9.2 DC Electrical Characteristics.............................................................................157 9.3 AC Electrical Characteristics .............................................................................158 Datasheet Multi-Protocol Communications Controller — CD2401 ......................................................................................157 5 ...
Page 6
... Transmit Data With External Clock In ................................................................. 64 13 Transmit Data With External Clock Out .............................................................. 64 14 DMA Connections for the CD2401...................................................................... 66 15 CD2401 Async Receive Character Processing................................................... 76 16 Initialization Sequence for the CD2401............................................................... 88 17 CLK/BUSCLK/RESET* Timing Relationship..................................................... 159 18 Slave Read Cycle Timing.................................................................................. 160 19 Slave Write Cycle Timing .................................................................................. 161 20 Interrupt Acknowledge Cycle Timing ...
Page 7
... SSPC[x] Settings.................................................................................................73 15 SCdet[x] Settings.................................................................................................74 16 Bisync Receive State Transition..........................................................................82 17 Description of States ...........................................................................................83 18 ETC Byte Sequence............................................................................................84 19 Byte Format — ETC Bit Set ................................................................................86 Datasheet Multi-Protocol Communications Controller — CD2401 7 ...
Page 8
... CD2401 — Multi-Protocol Communications Controller Revision History Revision Date 1.0 5/01 8 Description Initial release. Datasheet ...
Page 9
... Programmable translation of receiving character with error to different pattern (for example, character with parity error can be translated into FFh, 00h character on the system side) — Flow-control transparency and LNext • Programmable timer closely coupled with character reception, especially for asynchronous receive DMA operation Datasheet Multi-Protocol Communications Controller — CD2401 9 ...
Page 10
... CD2401 — Multi-Protocol Communications Controller Bisync Features • Programmable for ASCII or EBCDIC encoding • Support for transparent Bisync • Recognition of all special characters enabling: — Block separation — CRC generation and validation • Chaining of long receive blocks into multiple buffers X.21 Features • ...
Page 11
... FIFO depth (per channel and per direction) Data size (bits) Async SDLC/HDLC X.21, bisync Async-HDLC, PPP SLIP MNP 4 Serial data rate: sync / async (kbits/sec.) Datasheet Multi-Protocol Communications Controller — CD2401 RAM PROPRIETARY FIRMWARE RISC ROM PROCESSOR CD2231 CD2401 bytes 16 bytes – ...
Page 12
... A clock frequency of 35 MHz is required to obtain maximum bit-rates. 4. 134.4 kbps / 230.4 kbps in all async modes, 128 kbps / 256 kbps in sync modes: applies to Revision M or later CD2401; Revision D and later CD2431; Revision D or later CD2231. 5. UNIX character processing is available in Async mode only. ...
Page 13
... W The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘n/c’ indicates a pin that is a ‘no connect’. Datasheet Multi-Protocol Communications Controller — CD2401 Units of measure degree Celsius microfarad microsecond (1,000 nanoseconds) ...
Page 14
... CD2401 — Multi-Protocol Communications Controller Acronyms Acronym AC alternating current BCC block check character BRG bit rate generator bisync byte synchronous CMOS complementary metal-oxide semiconductor 1 CRC cyclic redundancy check DC direct current DCE data communication equipment DMA direct-memory access DPLL digital phase-locked loop ...
Page 15
... RTS*[2] 65 DSR*[3] 66 CTS*[3] 67 TXCOUT/DTR*[3] 68 RTS*[3] 69 GND 70 A[7] 71 A[6] 72 A[5] 73 A[4] 74 A[3] 75 A[2] 76 A[1] 77 A[0] 78 VDD 79 A/D[15] 80 Datasheet Multi-Protocol Communications Controller — CD2401 CD2401 18 100-Pin MQFP AEN* ...
Page 16
... CD2401 — Multi-Protocol Communications Controller 3.2 Pin Functions A[7:0] A/D[15:0] CLK CS* AS* DS* R/W* DTACK* SIZ[1:0] BUSCLK BERR* RESET* TEST ADLD* AEN* DATDIR* DATEN* BYTESWAP IACKIN* IACKOUT* IREQ*[3:1] BR* BGIN* BGOUT* BGACK* 3.3 Pin Descriptions The following conventions are used in the pin-description tables: • (*) after a pin name indicates that the signal is active-low • ...
Page 17
... DATA TRANSFER ACKNOWLEDGE*: When the CD2401 is not a bus master, this is an output and indicates to the host when a read or write to the CD2401 is complete. When BR* is driven low by the CD2401, DTACK input which indicates that the system bus is no longer in use ...
Page 18
... This pin is driven low during hardware reset. RESET*: This signal should stay valid for a minimum of 20 ns. The reset state I of the CD2401 is guaranteed at the rising edge of this signal. When RESET* is removed, the CD2401 also performs a software initialization of its registers. Description ...
Page 19
... RESET* pin can be driven low, and the TEST pin driven high or, • the CD2401 is kept in the bus idle state (not accessed for read/write operations nor DMA active), and the TEST pin is driven high. REQUEST TO SEND* [0–3]: This output can be controlled automatically by the O CD2401 to indicate that data is being sent on the TXD pin ...
Page 20
... CD2401 — Multi-Protocol Communications Controller Table 1. Pin Descriptions (Sheet Pin Symbol Type Number BYTESWAP 45, 79 20, 62, 70, GND 82 BYTESWAP: This pin alters the byte ordering of data during certain 16-bit transfers and changes the half of the data bus on which byte transfers are made to comply with Intel or Motorola processor systems ...
Page 21
... Register Table The registers in the CD2401 are either Global or Per-Channel. The column ‘Address mode’ in the memory map in the following tables defines this attribute for each register. Only one set of Global registers exists. The Global registers are accessible by the host at any time. Four sets of Per- Channel registers exist ...
Page 22
... CD2401 — Multi-Protocol Communications Controller 4.1.2 Option Registers Name Description CMR Channel Mode Register COR1 Channel Option Register 1 COR2 Channel Option Register 2 COR3 Channel Option Register 3 COR4 Channel Option Register 4 COR5 Channel Option Register 5 COR6 Channel Option Register 6 COR7 Channel Option Register 7 ...
Page 23
... Receive Interrupt Status Register RISRl Receive Interrupt Status Register low RISRh Receive Interrupt Status Register high RFOC Receive FIFO Output Count RDR Receive Data Register REOIR Receive End Of Interrupt Register Datasheet Multi-Protocol Communications Controller — CD2401 Addr INT MOT 1 Mode ...
Page 24
... CD2401 — Multi-Protocol Communications Controller 4.1.5.2 Transmit Interrupt Registers Name Description TPILR Transmit Priority Interrupt Level Register TIR Transmit Interrupt Register TISR Transmit Interrupt Status Register TFTC Transmit FIFO Transfer Count TDR Transmit Data Register TEOIR Transmit End Of Interrupt Register 4.1.5.3 Modem Interrupt Registers ...
Page 25
... A Transmit Buffer Byte Count BTBCNT B Transmit Buffer Byte Count ATBSTS A Transmit Buffer Status BTBSTS B Transmit Buffer Status TCBADRL Transmit Current Buffer Address Lower TCBADRU Transmit Current Buffer Address Upper Datasheet Multi-Protocol Communications Controller — CD2401 Addr INT MOT 1 Mode ...
Page 26
... CD2401 — Multi-Protocol Communications Controller 4.1.7 Timer Registers Name Description TPR Timer Period Register RTPR Receive Timeout Period Register RTPRl Receive Timeout Period Register low RTPRh Receive Timeout Period Register high GT1 General Timer 1 GT1l General Timer 1 low GT1h General Timer 1 high ...
Page 27
... Channel Option Register 3 (COR3) HDLC/Bisync Mode sndpad Alt1/S55 FCSPre Asynchronous Mode ESCDE RngDE FCT X.21 Mode SglSYN SSDE StrpSYN Channel Option Register 4 (COR4) DSRzd CDzd CTSzd Datasheet Multi-Protocol Communications Controller — CD2401 Ignore Chl3 Chl2 14 CRCNinv 0 RtsAO 0 RLM RtsAO CRCNinv SYN3 SYN2 ETC ...
Page 28
... CD2401 — Multi-Protocol Communications Controller Channel Option Register 5 (COR5) DSRod CDod CTSod Channel Option Register 6 (COR6) Asynchronous Mode IgnCR ICRNL INLCF Bisync Mode X.21 Mode Channel Option Register 7 (COR7) Asynchronous Mode IStrip LNE FCErr Special Character Register Special Character Register1 (SCHR1) Special Character Register2 (SCHR2) ...
Page 29
... H and later; earlier revisions, this bit is ‘0’. Special Transmit Command Register (STCR) 0 AbortTx AppdCmp Channel Status Register (CSR) HDLC Mode RxEn RxFlag RxFrame Datasheet Multi-Protocol Communications Controller — CD2401 Receive Bit Rate Period (Divisor) Dpllmd1 Dpllmd0 ClkSel2 Transmit Bit Rate Period (Divisor) res Ext-1X res RstAll EnTx ...
Page 30
... CD2401 — Multi-Protocol Communications Controller Asynchronous Mode RxEn RxFloff RxFlon Bisync Mode RxEn RxITB RxFrame X.21 Mode RxEn 0 RxSpc Modem Signal Value Registers (MSVR) Modem Signal Value Registers (MSVR-RTS) Modem Signal Value Registers (MSVR-DTR) DSR CD CTS Interrupt Registers Local Interrupt Vector Register (LIVR) ...
Page 31
... Receive Data Register (RDR Receive End Of Interrupt Register (REOIR) TermBuff DiscExc SetTm2 4.2.4.2 Transmit Interrupt Registers Transmit Priority Interrupt Level Register (TPILR) Transmit Interrupt Register (TIR) Ten Tact Teoi Datasheet Multi-Protocol Communications Controller — CD2401 8A 8A CRC OE Reslnd SCdet0 OE PE CRC OE 0 SCdet0 ...
Page 32
... CD2401 — Multi-Protocol Communications Controller Transmit Interrupt Status Register (TISR) Berr EOF EOE Transmit FIFO Transfer Count (TFTC Transmit Data Register (TDR Transmit End Of Interrupt Register (TEOIR) TermBuff EOF SetTm2 4.2.4.3 Modem/Timer Interrupt Registers Modem Priority Interrupt Level Register (MPILR) ...
Page 33
... EOF EOB Transmit Current Buffer Address Lower (TCBADRL) Transmit Current Buffer Address Upper (TCBADRU) 4.2.6 Timer Registers Timer Period Register (TPR) Receive Timeout Period Register (RTPR) Receive Timeout Period Register low (RTPRl) Datasheet Multi-Protocol Communications Controller — CD2401 ...
Page 34
... CD2401 — Multi-Protocol Communications Controller Receive Timeout Period Register high (RTPRh) General Timer 1 (GT1) General Timer 1 low (GT1l) General Timer 1 high (GT1h) General Timer 2 (GT2) Transmit Timer Register (TTR Binary Value, bits 15 R/W Async Sync Sync ...
Page 35
... CLK and BUSCLK signals possible, however, to use the CD2401 in a purely asynchronous bus environment. The CD2401 can act as either bus master during DMA transfers bus slave device during normal host read and write transfers. Both byte and word transfers are supported in each of the Bus Slave and DMA Bus Master modes ...
Page 36
... CD2401 — Multi-Protocol Communications Controller Figure 2. Host Read Cycle CS* DS* R/W* A/D[15:0] A[7:0], SIZ[1:0] DTACK* DATEN* DATDIR* 36 DOUT Datasheet ...
Page 37
... DATDIR* 5.1.2 Byte and Word Transfers Data can be moved to and from the CD2401 in either byte or word transfers. To accommodate various families of host processors, the BYTESWAP input pin is set to indicate the system byte- ordering scheme. SIZ[1:0] indicate whether the transfer bytes wide. ...
Page 38
... TDR and RDR provide access to the FIFO buffers for each channel. These registers must not be accessed outside of the proper interrupt context. A write operation to the End of Interrupt registers (REOIR, TEOIR, or MEOIR) must be the last access to the CD2401 at the end of this handler routine to return it to its background context. ...
Page 39
... Groups and Types There are two general reasons for the CD2401 to request service from the host processor — data transfer and exceptional conditions. Furthermore, interrupts are grouped into three categories, each with an associated Interrupt Request signal — IREQ1*, IREQ2*, and IREQ3*. ...
Page 40
... CD2401 — Multi-Protocol Communications Controller Interrupt Vector LSBs 00 Receive exception 01 Modem signal change or timer event 10 Transmit data or exception 11 Receive Good Data 40 Datasheet ...
Page 41
... DTACK* is asserted. DTACK* is released after DS* is removed. Figure 4 on page 39 read cycle except that IACKIN* is active, and CS* is inactive. The three IREQn* pins are open-drain outputs requiring external pull-up resistors, nominally 4.7 k¾. The IACKOUT* is used to form a daisy-chain in systems with more than one CD2401 (see Section 5.2.5). 5.2.4.1 ...
Page 42
... CD2401s in the system are presented to the host with equal urgency. There is no positional hierarchy in the interrupt scheme, that is, the CD2401 farthest from the host has as equal a chance of getting its interrupts through as that of the CD2401 nearest to the top of the interrupt chain. The Fair Share scheme is transparent to the user, and no enabling or disabling is required. ...
Page 43
... The TxEmpty and TxD bits (IER[1:0]) control the generation of transmit FIFO interrupts. The CD2401 initiates an interrupt request for more data when the number of empty bytes in the FIFO is greater than the threshold set. During synchronous operation when the last byte of the frame is transferred to the FIFO, the CD2401 stops asserting transmit interrupts until the frame is sent ...
Page 44
... When transmitting, the host processor alternately fills the A and B buffers, and commands the CD2401 to transmit the buffers one at a time. When receiving, the CD2401 fills the A and B buffers and informs the host processor when each is ready. A simple Ownership Status bit is used for each buffer ...
Page 45
... If BGACK* is high when BGIN* goes low, then the bus is free to access step BGACK* is low when BGIN* goes low, then the bus is in use. The CD2401 waits for BGACK high. 5. Once the CD2401 senses that BGACK* is high, it waits for the current bus cycle to terminate (DS* and DTACK* high), then asserts BGACK* by driving it low. At that time, the CD2401 ‘ ...
Page 46
... Bus Error Handling When a bus error is detected during a DMA sequence, the CD2401 terminates the current bus cycle and relinquishes the bus. Any data transfer in the bus ownership cycle is ignored and the original conditions are restored. A subsequent retry attempt would start again from these original conditions ...
Page 47
... EOF bit is set, the CRC and closing flag/syn are appended, and the next buffer is again treated as the start of frame. If the EOF bit is not set, the CD2401 treats the buffer as the first part of a larger frame and chains into the next buffer (does not reset CRC); this process continues until a buffer is supplied with the EOF bit set ...
Page 48
... Append mode transfers are available for buffer A in Asynchronous mode only. If buffer A is set to Append mode, the host can enable the CD2401 to transmit data in the buffer before it is completely filled. The CD2401 starts transmitting new data when it is appended to the buffer. ...
Page 49
... The CD2401 completes frame transmission by adding any necessary CRCs and trailing-frame delimiters. 6. When the CD2401 completes the transmission, it clears the Tbusy bit. Then it sets the EOB bit and clears the 2401own bit (ATBSTS[0]). This notifies the host that the transmission is complete, and the CD2401 returns ownership of the buffer back to the host. ...
Page 50
... A is next. This helps the host keep track of which buffer is next. As transmission progresses, the current buffer pointer (TCBADR) is updated by the CD2401. During or prior to this, the host has readied buffer A. For buffer A, the EOF bit (ATBSTS[6]) is cleared by the host, indicating that the buffer is not the end of the chain. ...
Page 51
... CD2401 is now free to use the buffer for receive data, and update the appropriate Buffer Status register. When the buffer is no longer in use, the CD2401 writes the number of bytes stored in the buffer in RBCNT and updates status in RBSTS. This frees the host to take control of this buffer and supply a new buffer in its place ...
Page 52
... CD2401 has written the actual byte count of the received buffer into ARBCNT.) 6. The CD2401 sets the EOB and EOF bits. This notifies the host that the end of the buffer and frame have been reached. The CD2401 also clears the 2401own bit to return the buffer to the host ...
Page 53
... CD2401, the value of 40 (for 40 received bytes) is written into the received byte count (BRBCNT). 15. Next, the CD2401 sets the EOB and EOF bits to show that the buffer is complete, and that this is the last link in the chain. 16. The CD2401 optionally interrupts the host with EOF and EOB set (RISRh[6:5]) to indicate that the received frame is complete, and this was the last link in the chain ...
Page 54
... CPU. When the bit is clear, the descriptor is owned by the CPU. When DMA is selected and the channel is enabled, the CD2401 waits for ownership of buffer A. When ownership given by setting the 2401own bit, the buffer is transmitted and the ownership bit is cleared. The CD2401 waits for ownership of buffer B ...
Page 55
... Figure 9. DMA Transmit Buffer Selection Update Descriptor and Set 2401own N More Data to Send ? Datasheet Multi-Protocol Communications Controller — CD2401 Start Read DMABSTS to Determine Next Transmit Buffer (NtBuf) Next Buffer 0 1 2401own Bit ? Y 0 Other Buffer 2401own Bit Update Descriptor and Set 2401own ...
Page 56
... ATBCNT. The CD2401 can now scan the ATBCNT register for any changes; if new data is found read from the buffer and transmitted. When no more data is found in the Append buffer, the CD2401 scans the B buffer for ownership. If the B buffer is owned by the CD2401, then the data in that buffer is transmitted uninterrupted; at the end of the transmission, the A buffer count continues to be scanned for new data ...
Page 57
... Receive Timeout in Asynchronous DMA Mode In Asynchronous DMA mode, the only way that the CD2401 releases the ownership is reaching the end-of-buffer. Receive timeout, or any exceptions, do not release the ownership if end-of-buffer condition is not met. The following illustrates recommended procedures to handle a receive timeout in Asynchronous DMA mode. Scenario 1: Buffer A is currently selected ...
Page 58
... Bit Rate Generation and Data Encoding BRG and DPLL Operation Data clocks are generated in the CD2401 by feeding one of a number of clock sources into a programmable divider. The clock source and divisor are user-programmable separately for each channel and direction. Clock options are programmed in TCOR and RCOR. The divisors are programmed in TBPR and RBPR ...
Page 59
... Value loaded into RCOR = 06h, to select External Clock mode Value loaded into TCOR = C0h, to select External Clock mode †. R/T is used as a register abbreviation indicating Receive / Transmit followed by the register acronym. Datasheet Multi-Protocol Communications Controller — CD2401 Frequency of chosen clock source = -------------------------------------------------------------------------------- - 1 Desired bit rate † ...
Page 60
... CD2401 — Multi-Protocol Communications Controller Figure 10. BRG and DPLL System Clock 8 Clk 0 32 Clk 1 128 Clk 2 512 Clk 3 2048 Clk 4 RXCin or TXCin RX bit clk (for TX BRG only) Receive Clock Option Register (RCOR) TLVal res dpllEn Transmit Clock Option Register (TCOR) ClkSel2 ...
Page 61
... Table 6. Bit Rate Constants, CLK = 25 MHz (Sheet Bit Rate 50 110 150 300 600 1200 2401 3600 4800 7200 9600 Datasheet Multi-Protocol Communications Controller — CD2401 ClkSel0 Select 0 External clock 1 Reserved 1 Receive clock 1 Divisor Clock c2 Clk 4 58 ...
Page 62
... CD2401 — Multi-Protocol Communications Controller Table 6. Bit Rate Constants, CLK = 25 MHz (Sheet Bit Rate 19200 38400 56000 64000 76800 1.All divisors are in hexadecimal. Table 7. Bit Rate Constants, CLK = 30 MHz Bit Rate 110 150 300 600 1200 2401 3600 4800 7200 ...
Page 63
... CLK input divided by 16, (that is, for 33-MHz operation, the data clock should be less than 2 MHz). Note that R/TBPR are 8-bit registers; therefore the largest divisor value is 255. Use the following equation to compute the divisor value. Datasheet Multi-Protocol Communications Controller — CD2401 1 Divisor Clock ...
Page 64
... CD2401 — Multi-Protocol Communications Controller Bit rate divisor Figure 11. Data Encoding Figure 12. Transmit Data With External Clock In Note: When using the external receive clock in Receive mode, data is sampled on the low-to-high going edge of RXCIN. Figure 13. Transmit Data With External Clock Out ...
Page 65
... The common control lines (ADLD*, AEN*, DATDIR*, DATEN*) to the external devices are wire-OR’ed together. These pins are tristate, not open collector, but an external pull-up resistor (2.2–5.0 k¾) must be connected to each line to ensure logic 1 when no CD2401 is a bus master. When no higher-priority alternate bus masters are present, a daisy-chain priority scheme can be implemented by wire OR’ ...
Page 66
... D[0–15] pins from either half of the 32-bit bus. The A[1] address pin determines if the lower or upper half of the data bus is in use for a particular bus cycle. The CD2401 always drives all 16 data bits during a register read or a DMA write operation, regardless of the size of the actual transfer. ...
Page 67
... RXD TXD RTS* CTS* DSR* TXCOUT/DTR* RXCIN TXCIN RXCOUT CD* Table 11 shows the recommended DCE (data communication equipment) connections between the CD2401 and RS-232C, X.21, and X.21 bis standard interfaces. Table 11. DCE Connections CD2401 RXD TXD RTS* CTS* DSR* TXCOUT/DTR* RXCIN TXCIN RXCOUT CD* † ...
Page 68
... Frame Check Sequence FCS is a 16-bit standard computation used in HDLC and defined in ISO 3309. This FCS algorithm is the same used with the synchronous HDLC operation of the CD2401. The basic characteristics of the FCS are the following: Accumulation: FCS computation starts after the opening flag and continues to the closing flag. ...
Page 69
... DMA transfers or Good Data interrupts, and then an EOF (End of Frame) interrupt is generated. The CRC can be either validated or ignored. If the CD2401 does not check the CRC passed onto the host. A validated CRC can be discarded or passed onto the host for diagnostic purposes. The next non-flag/abort character restarts the process ...
Page 70
... CD2401 — Multi-Protocol Communications Controller Indication (0, off) from the remote. If detected, the remainder of the current frame is discarded, and a clear-detect indication is passed to the CPU by the RISR. However, the channel remains in HDLC mode until modified by the CPU. 6.2 Async Processing Data is transmitted according to the format options defined in the CORs. These options determine the character length, parity, and Stop bit length ...
Page 71
... CD2401 sets the DTR* pin high. When the data in the FIFO falls below the DTR* threshold, the DTR* pin is automatically driven low. Each channel of the CD2401 has four pins that can be used either as a modem control or general- purpose input/output pins. The modem signal names assigned to these four pins were selected to provide an easy reference for system designers ...
Page 72
... CTS For example, if the CD2401 is designed to be DCE and automatic out-of-band flow control is desired, connect the DTR pin to the remote CTS input. If the CD2401 used as the DTE side, then connect the CD2401 CTS output to the remote CTS input. Note that if automatic out-of-band flow control is implemented, the activity of the DTR and DSR pins do not implement the function assigned to those signal names by the signaling conventions of the CCITT and other standards organizations ...
Page 73
... Special Characters Special Character Transmission Selected special characters can be sent preemptively by setting the SndSpc bit (STCR[3]). The CD2401 channel acknowledges the command by clearing the STCR. Along with the SndSpc bit, the host needs to setup the three SSPC bits (STCR[2:0]) to select which character sent. ...
Page 74
... But overrun condition occurred after a special character was detected, the new character is lost and the overrun status is set. In this condition, the CD2401 gives both an overrun exception and a special character recognition status. 6.2.7 Special Character Range The SCRs define an inclusive range for special character recognition in Asynchronous mode ...
Page 75
... CPU as a normal character. The LNext character is programmed by the LNext register. The ‘strip’ feature (COR7[7]) strips the eighth bit off each error-free received character. This has no effect on the transmitted data. order of the CD2401 character processing steps and the receive character processing flow for Async mode in flowchart format. Datasheet Multi-Protocol Communications Controller — ...
Page 76
... CD2401 — Multi-Protocol Communications Controller Figure 15. CD2401 Async Receive Character Processing CHARACTER RECEIVED N ERROR? Y ISTRIP COR7[7] Y FCErr COR7[5] N LNE COR7[6] Y PREVIOUS CHAR = LNXT N IStrip COR7[7] N SCDE COR3[4] N ESCDE COR3[ ZERO COR7[ ZERO COR7[7] FOR SPECIAL CHAR MATCH ONLY ...
Page 77
... Figure 15. CD2401 Async Receive Character Processing (Continued CHAR = BREAK Y Process Break Options IgnBrk NBrkInt DONE Datasheet Multi-Protocol Communications Controller — CD2401 COR6 Action Exception interrupt Discard character Replace with 0 Process Parity Options ParMrk INPCK ParInt ...
Page 78
... CD2401 — Multi-Protocol Communications Controller Figure 15. CD2401 Async Receive Character Processing (Continued) B RngDE Y COR3[6] N CR/NL Y OPTIONS COR6[6] N CHAR SCRL Y EXCEPTION CHAR INTERRUPT SCRH N CHAR = DISCARD Y Y CHAR CR/ PROCESS TRANSLATION OPTIONS CHAR TO FIFO ParMrk Y ADD EXTRA COR6[ FIFO ...
Page 79
... If a frame transmission is aborted by the STCR, an EOT and a trailing pad are transmitted and the line returned to its idle state. A frame is terminated normally when an EOF indication is passed to the CD2401, either in TEOIR or in A/BTBSTS. If the frame ends with an EOT or ENQ condition, the trailing pad is appended and transmission is complete; otherwise, any accumulated BCC is appended followed by the trailing pad, and the line returns to the idle state ...
Page 80
... STX and ENQ are passed to host as data. 6.3.3 CRC Calculation in Bisync Mode In Bisync mode there are several conditions where the CD2401 varies the way it computes the FCS or BCC/CRC. Which data is included in the current frame depends on how the previous frame ended and the transparency in the middle of a frame. ...
Page 81
... On receive, the CD2401 checks CRC according to the previous illustrations and strips the DLE from the data stream. 6.3.4 BCC Computation Formulas In Bisync mode, the CD2401 can use either CRC-16 or LRC. The mode used is determined by the setting of the LRC bit (COR2[7]). CRC-16 uses the polynomial in the following equation, preset to all zeroes. x**16 + x**15 + x** LRC performs a parity check on each bit of each character in the frame in a longitudinal or ‘ ...
Page 82
... CD2401 — Multi-Protocol Communications Controller Note:If parity is used, parity is computed/checked on each character, but the LRC of the parity bits is not checked. 6.3.5 Receive State Table Table 16 on page 82 receive microcode character processing, and the definition of the states. Table 16. Bisync Receive State Transition BGETHDR ...
Page 83
... To minimize CPU intervention in the transmit direction, a modified version of the ETC is used. ETC mode is controlled through COR2. When enabled, ETC mode provides a means of transmitting steady state or repetitive data patterns synchronized to the control lead. The ETC consists of a sequence of four bytes passed to the CD2401 as normal transmit data, in the format shown in Table 18 ...
Page 84
... X.21 Receive In receive, the CD2401 validates the steady-state conditions, passing just the change-of-state information to the CPU. Steady-state conditions validated are: • all ‘1’s • ...
Page 85
... In these conditions, the partial character is passed to the host as normal data. Note: The CD2401 passes all data received to the host before it receives SYN characters. Example Assume the SSDE, StrpSYN, and SCDE bits are set, that is the CD2401 detects steady-state conditions, strip SYN characters, and special characters from the incoming data ...
Page 86
... If set to ‘0’, the character is sent until new data is supplied. Byte 4 In this case, the CD2401 always sends the data a minimum of three times, even if new data is made available before all three characters are sent. To idle in mark with the RTS* line off, write the command ‘ 00’. To send the character ‘ ...
Page 87
... For HDLC mode, 8-bits per character are always transmitted. The CD2401 transmits only byte- aligned frames. The CD2401 receives HDLC frames using transfers of 8 bits per character, except for the last character received before the FCS. If this last character is not aligned to an 8-bit boundary, the ResInd and EOF bits (RISRl[2, 6]) are set ...
Page 88
... CD2401 — Multi-Protocol Communications Controller 7.0 Programming Examples This section provides some examples of CD2401 programming. Included are examples of Global and Per-Channel initialization, and two interrupt service routines. The code was written in Borland Turbo C . Figure 16. Initialization Sequence for the CD2401 DO NOT ISSUE A ‘RESET ALL’ COMMAND ...
Page 89
... The TPR loads the dividing counter that provides input to each of the other timers in the CD2401. The DMA Mode and Bus Error Count registers are used in DMA modes only. After the global portion is done, the Per-Channel registers need to be initialized. ...
Page 90
... DMA transfers. The normal exception is when an end-of-frame is received. The DMABSTS register shows which buffer the CD2401 expects to use next. Fill the descriptor registers for that buffer, including the 2401own bit and return. The last access to the CD2401 during the service routine is the REOIR. int risrl = inportb( RISRL ); ...
Page 91
... TDR, ob[ch].nxt_char() );//send next character } } outportb( TEOIR, teoir ); Datasheet Multi-Protocol Communications Controller — CD2401 // shouldn’t happen in DMA // EOF is ’normal’ exception if( inportb(DMABSTS) & DMABS_NRBUF ) // get next buffer // buffer A next // get next buffer // default // status ...
Page 92
... This register serves two functions in providing the host with information about the CD2401. When the CD2401 is initialized by a hardware RESET* signal software ‘Reset All’ command issued through any CCR, the CD2401 zeros this register at the start of the initialization. At the conclusion of the initialization, the CD2401 writes the firmware revision code to the GFRCR. All valid CD2401 revision codes are non-zero, the revision code is incremented by one with each new release (for example, GFRCR for Revision hex) ...
Page 93
... Interrupt 1 = DMA Bit 6 Transmit Transfer Mode 0 = Interrupt 1 = DMA Bits 5:3 Reserved – must be ‘0’. Bits 2:0 Protocol mode select [2:0] If these options are changed, an initialization command must be given to the CD2401 through the CCR. chmd2 Datasheet Multi-Protocol Communications Controller — CD2401 C1 C0 Channel Number 0 0 ...
Page 94
... Access: Byte Read/Write Bit 7 Bit 6 Bit 5 AFLO ClrDet AdMde1 An Initialization command must be given to CD2401 through the CCR if any options specified in this register are changed. Bit 7 Address Field Length Option 0 = address field is one octet in length 1 = address field is two octets in length Bit 6 Clear Detect for X.21 data transfer phase ...
Page 95
... Parity mode 1 and 0 – Defines Parity mode for both transmitter and receiver. ParM1 Bit 4 Ignore parity 0 = evaluate parity on received characters parity evaluation of received characters. Bits 3:0 Character Length [3:0] Chl3 Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Ignore Chl3 ParM0 0 0 None 0 1 Force (odd parity = force 1, even = force ...
Page 96
... Bit 2 RTS Automatic Output enable When this bit is set and the channel is enabled, the CD2401 automatically asserts the RTS* output when it has characters to send. When Idle in Mark mode is selected, RTS* is asserted prior to opening flags and remains asserted until after a closing flag has been transmitted ...
Page 97
... RTS* output pin remains enabled during DMA or character bursts from the transmit FIFO. If the CTS* input pin goes high, then RTS* goes high and transmis- sion stops after the current burst is complete. Bit 1 CTS* Automatic Enable 0 = the transmitter output enable is independent of the CTS* input pin. Datasheet Multi-Protocol Communications Controller — CD2401 97 ...
Page 98
... CD2401 — Multi-Protocol Communications Controller 1 = CTS* is evaluated prior to the transmission of each character. If CTS* is asserted low, that character is transmitted completely. If CTS* is high, that character trans- mission is held until CTS* goes low. Bit 0 DSR* Automatic Enable 0 = the receiver input enable is independent of the DSR* input pin. ...
Page 99
... Byte 4 This is the count of the number of times the character should be sent. If set to ‘0’, the character is sent continuously until more data is provided to the transmitter (but always a minimum of three times). Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit Section 6 ...
Page 100
... DPLL at the remote end. The pad character (00h or AAh) sent depends on the type of encoding used. Bit 7 Send Pad character 0 = CD2401 does not send any pad character CD2401 sends pad character(s) before sending flag when coming out of the Idle In Mark mode. Bit 6 Send sync pattern 0 = 00h is sent as pad character (NRZI encoding). ...
Page 101
... The character passed to the host is unaffected. This function allows special character processing of data without knowing if the data is 8-bits no parity or 7-bits with parity. Bits 2:0 Stop bit length [2:0] These bits specify the length of the Stop bit. Datasheet Multi-Protocol Communications Controller — CD2401 pad2 pad1 pad0 ...
Page 102
... S55 FCSPre Bit 7 Send Pad character 0 = CD2401 does not send any pad characters CD2401 sends pad characters before sending SYN when coming out of the Idle- In Mark mode. Bit 6 Send pad pattern 0 = hex AA is sent as pad character hex 55 is sent as pad character. ...
Page 103
... To be detected as a special condition, a change must be present for at least 16-bit times. When detected, a receive exception interrupt is generated with the relevant status set in the RISR. After detection of the special condition, no further data is passed to the host until different data is received. Datasheet Multi-Protocol Communications Controller — CD2401 pad2 pad1 pad0 0 ...
Page 104
... CD2401 — Multi-Protocol Communications Controller There is no character synchronization in certain phases of X.21 call setup. When a data change occurs in a non-character synchronous phase, a partial character can be detected before the steady state is detected or character sync is achieved. In these conditions, the partial character is passed to the host as normal data. ...
Page 105
... FIFO is greater than the specified threshold. An EPF is also cause to initiate a receive transfer. For transmit operation, the CD2401 attempts to refill the transmit FIFO when the empty space in the FIFO is greater than the set threshold. In the case of synchronous frame transmissions, the CD2401 stops refilling the transmit FIFO once the last character in the frame transfers to the FIFO ...
Page 106
... CD2401 — Multi-Protocol Communications Controller 8.2.7 Channel Option Register 6 (COR6) COR6 — Async Mode Register Name: COR6 Register Description: Channel Option 6 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 IgnCR ICRNL INLCF CR is defined as 0D hex hex, and NULL as 00 hex. ...
Page 107
... BCC is received as data and the idle line condition causes the frame to terminate. The idle line character is the last character in the frame. No attempt is made to perform a CRC on the receive data under these conditions. Note: This feature is not available in revisions prior to Revision ‘H’. Datasheet Multi-Protocol Communications Controller — CD2401 INPCK ParInt Generated an exception interrupt ...
Page 108
... CD2401 — Multi-Protocol Communications Controller COR6 — X.21 Mode Register Name: COR6 Register Description: Channel Option 6 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 In X.21 mode, this register contains the character to be used for find character synchronization with the receive datastream. When the initialize channel command in the CCR is processed, COR6 is set to the value ASCII SYN (hex 16) ...
Page 109
... LNE provides a mechanism to transfer flow control and special characters as normal data, without invoking flow control action in the CD2401 and without generating special interrupts. The LNext character is defined in the LNXT register and, when processed, is always passed to the host CPU as normal data. Bit 5 ...
Page 110
... CD2401 — Multi-Protocol Communications Controller 8.2.9.2 Special Character Register 2 (SCHR2) Register Name: SCHR2 Register Description: Special Character 2 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 SCHR1 and 2 are used in conjunction with the SCDE bit (COR3[4]) to detect specific incoming characters. When both the SCDE and TxIBE (COR2[6]) bits are set, they define the in-band flow control characters XON and XOFF ...
Page 111
... Bit 6 Bit 5 This register defines the LNext character. If the LNext function is enabled (COR7[6]), the CD2401 examines received characters and compares them against this value match occurs, this character and the next are placed in the FIFO without any special processing. In effect, the LNext function causes the CD2401 to ignore characters with special meaning, such as flow control characters ...
Page 112
... CD2401 — Multi-Protocol Communications Controller 8.2.12 Receive Frame Address Registers (RFAR) — HDLC Sync Mode only 8.2.12.1 Receive Frame Address Register 1 (RFAR1) Register Name: RFAR1 Register Description: Receive Frame Address 1 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 8.2.12.2 Receive Frame Address Register 2 (RFAR2) ...
Page 113
... external clock is used, a value of 01h must be loaded in the RBPR. Datasheet Multi-Protocol Communications Controller — CD2401 page 94 Bit 4 Bit 3 Bit 2 ...
Page 114
... CD2401 — Multi-Protocol Communications Controller 8.3.1.2 Receive Clock Option Register (RCOR) Register Name: RCOR Register Description: Receive Clock Option Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 TLVal 0 DpllEn This register is used to select the DPLL mode and the desired clock source for the receive BRG. ...
Page 115
... This register controls the transmit BRG and Local Loopback mode. Bits 7:5 Clock Select [2:0] These bits select the clock source for the transmit BRG. Note: See the detailed description of clock options in Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Transmit Bit Rate Period (Divisor) Bit 4 Bit 3 ...
Page 116
... The various command and control bits in this register perform largely independent functions. The host can assert multiple command bits to achieve the desired effect. The CD2401 clears the register to ‘1’ after it accepts and acts on a host command. The host must verify that the contents of this register are ‘ ...
Page 117
... For mode 1, this bit must be ‘0’. Bit 6 Clear Channel command When this command is issued, the CD2401 clears the data FIFOs and current trans- mit and receive status of the channel in the CSR. If the channel is currently transmit- ting a frame in synchronous protocol, the host should issue the Transmit Abort special transmit command prior to issuing a clear command ...
Page 118
... RcvEn bit. ClrRcv clears the receive DMA buffer status in A/BRBSTS and receive status in DMABSTS. Clearing the 2401own bits in both Receive Buffer Status reg- isters means that DMA buffers must be returned to the CD2401 before receive trans- fers can begin again. For Synchronous modes, this command puts the receiver back into SYN/Flag Hunt mode. Note: This command is not available in revisions prior to Revision ‘ ...
Page 119
... Bit 7 Bit 6 Bit 5 0 AbortTx AppdCmp The CD2401 clears STCR to ‘0’ when it accepts a host CPU command. Bit 7 Reserved – must be ‘0’. Bit 6 Abort Transmission (HDLC mode) This bit terminates the frame currently in transmission with an abort sequence. In DMA mode, all data up to the next EOF is discarded. ...
Page 120
... CD2401 — Multi-Protocol Communications Controller HDLC Mode Register Name: CSR Register Description: Channel Status Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 RxEn RxFlag RxFrame Bit 7 Receiver Enable 0 = receiver disabled receiver enabled. Bit 6 Receive Flag 0 = currently not receiving flag/SYN currently receiving flag/SYN. ...
Page 121
... CD2401 receives a request to resume transmission, the transmitter is enabled/disabled, or the channel is reset. Bit 1 Transmit Flow normal 1 = the CD2401 was requested by the remote to resume transmission. This bit is reset once character transmission is resumed, the transmitter is enabled/disabled, or the channel is reset. Bit 0 Reserved – always returns ‘0’ when read. ...
Page 122
... This bit is set if the last frame transmitted ended with an ITB character (that is, the leading character of the next frame is included in the BCC calculation). Bit 1 Transmit Frame status When this bit is set, it indicates that the CD2401 is currently transmitting a frame. Bit 0 Reserved – always returns ‘0’ when read. X.21 Mode ...
Page 123
... Bit 6 Reserved – always returns ‘0’ when read. Bit 5 Receive Special When this bit is set, it indicates that the CD2401 is currently in a steady-state condi- tion. Such conditions generate a receive special character interrupt. Bit 4 Reserved – always returns ‘0’ when read. ...
Page 124
... The host effectively controls bits 7:2; the device provides bits 1:0 within an interrupt acknowledge context. The CD2401 has one Local Interrupt Vector register per channel, each with six host-defined bits. The host can opt to embed the channel number and the protocol in use in the channel vector. The CD2401 supplies two modified bits signifying the type of interrupt service required ...
Page 125
... Note: Because the CD2401 provides a unique Local Interrupt Vector register for each channel, the host has the option to include the channel number within the interrupt vector. 8.5.1.2 Interrupt Enable Register (IER) Register Name: IER Register Description: Interrupt Enable Default Value: x’00 Access: Byte Read/Write ...
Page 126
... CD2401 — Multi-Protocol Communications Controller Bit 0 Transmit Data Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer mode. Group 2 interrupts are generated at the end of transmit DMA buffers or when the FIFO threshold is reached in Interrupt Transfer mode. 8.5.1.3 Local Interrupting Channel Register (LICR) Register Name: LICR ...
Page 127
... Bit 5 This register must be initialized by the host to contain the codes that are presented on the address bus by the host system to indicate which of the three CD2401 interrupt types (that is, modem, transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2401 compares bits 0–6 in this register with A[6:0] to determine if the acknowledge level is correct. The value programmed in the MSB of the register has no effect on the IACK cycle ...
Page 128
... Unused – always returns ‘0’ when read. Bits 3:2 Receive Vector [1:0] These bits are set by the CD2401 to provide the lower 2 bits of the vector supplied to the host CPU during an interrupt acknowledge cycle. The Receive Good Data vector is decoded as: Rvct [ Rvct [ The Receive exception vector is decoded as: Rvct [ Rvct [ ...
Page 129
... Bit 3 Overrun Error This bit indicates that new data has arrived, but the CD2401 FIFO or Holding regis- ters are full. The new data is lost, and the overrun indication is flagged on the last character received before the overrun occurred. In HDLC and Bisync modes, the remainder of a frame following an overrun is discarded ...
Page 130
... Special Character Detect [2:0] SCdet2 Bit 3 Overrun Error This bit indicates that new data has arrived, but the CD2401 FIFO or Holding regis- ters are full. The new data is lost and the overrun indication is flagged on the last character received before the overrun occurred. Bit 2 Parity Error This bit indicates that a parity error occurred ...
Page 131
... For X.21 operation, the CTS* pin is used as the ‘I’ lead for DTE or ‘C’ lead for DCE; a low level on CTS* is interpreted condition and a high level as an OFF condition. Bit 7 Lead Value 0 = OFF Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 CRC OE 0 ...
Page 132
... Access: Byte Read only Bit 7 Bit 6 Bit 5 Berr EOF EOB Note: This register is used in DMA mode only. Bit 7 Bus Error (written by CD2401 bus error bus error detected on last transfer. The actual address at which the error occurred 132 SCdet2 SCdet1 ...
Page 133
... Receive Data Register (RDR) Register Name: RDR Register Description: Receive Data Default Value: x’00 Access: Byte Read only Bit 7 Bit 6 Bit Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 RxCt4 RxCt3 RxCt2 Bit 4 Bit 3 Bit Intel Hex Address: x’33 Motorola Hex Address: x’ ...
Page 134
... DiscExc SetTm2 This must be written to by the host receive interrupt service routine to signal to the CD2401 that the current interrupt service is concluded. This must be the last access to the CD2401 during an interrupt service routine. A write to this register generates an internal end-of-interrupt signal that pops the CD2401 interrupt context stack ...
Page 135
... Bit 5 This register must be initialized by the host to contain the codes that are presented on the address bus by the host system to indicate which of the three CD2401 interrupt types (that is, modem, transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2401 compares bits 0–6 in this register with A[0–6] to determine if the acknowledge level is correct. The value programmed in the MSB of this register has no effect on the IACK cycle ...
Page 136
... Unused – always returns ‘0’ when read. Bits 3:2 Transmit Vector [1:0] These bits are set by the CD2401 to provide the least-significant two bits of the vec- tor supplied to the host CPU during an interrupt acknowledge cycle. Transmit vector is decoded as: Tvct [ and Tvct [ ...
Page 137
... Interrupt Transfer mode. Data must be written as bytes, and follows the rules for positioning valid data on the bus as outlined in high, data must be valid on A/D[7:0]; if BYTESWAP is low, data must be valid on A/D[15:8] because the TDR even address. Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 TxCt4 ...
Page 138
... SetTm2 This register must be written to by the host transmit interrupt service routine to signal to the CD2401 that the current interrupt service is concluded. This must be the last access to the CD2401 during an interrupt service routine. A write to this register generates an internal end-of-interrupt signal that pops the CD2401 interrupt context stack. ...
Page 139
... Bit 5 This register must be initialized by the host to contain the codes that are presented on the address bus by the host system to indicate which of the three CD2401 interrupt types (that is, modem, transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2401 compares bits 6:0 in this register with A[6:0] to determine if the acknowledge level is correct. The value programmed in the MSB of this register has no effect on the IACK cycle ...
Page 140
... Unused – always returns ‘0’ when read. Bits 3:2 Modem Vector [1:0] These bits are set by the CD2401 to provide the least-significant two bits of the vec- tor supplied to the host CPU during an interrupt acknowledge cycle. Modem vector is decoded as follows: Mvct [ and Mvct [ ...
Page 141
... Reserved – must be ‘0’. At the end of an interrupt service routine, the user can set one of the timers by setting a timer value in the MISR and setting the appropriate bit in this register. When the timer reaches zero, the CD2401 generates a modem/timer group interrupt to the host. 8.6 DMA Registers 8 ...
Page 142
... DMA operations suspended to the buffer in error, until the interrupt is processed by the host CPU. When this register contains a non-zero value and when a bus error occurs, the CD2401 retries the same DMA operation and decrements the register value by one. When the value reaches zero, the next bus error causes an interrupt, at which time a new count can be loaded by the host CPU ...
Page 143
... Default Value: x’0000 Access: Word Read/Write Bit 15 Bit 14 Bit 13 Bit 7 Bit 6 Bit 5 Datasheet Multi-Protocol Communications Controller — CD2401 Bit 12 Bit 11 Binary Address Value, 32-bit Address bits 15:8 Bit 4 Bit 3 Binary Address Value, 32-bit Address bits 7:0 Intel Hex Address: x’40 Motorola Hex Address: x’42 ...
Page 144
... Bit 13 Bit 7 Bit 6 Bit 5 This register contains the start addresses of the A external buffer used by the CD2401 to store the receive data block. This register is written to by the host and copied internally to control the data transfer to the memory. 8.6.4.3 B Receive Buffer Address – Lower (BRBADRL) Register Register Name: BRBADRL Register Description: Receive Buffer ‘ ...
Page 145
... Bit 13 Bit 7 Bit 6 Bit 5 This register contains the start addresses of the B external buffer used by the CD2401 to store the receive data block. This register is written to by the host and copied internally to control the data transfer to the memory. 8.6.4.5 A Buffer Receive Byte Count (ARBCNT) Register ...
Page 146
... Bit 6 Bit 5 These registers contain the number of bytes stored in the external data buffers by the CD2401. The count is updated after a block of data is moved to memory and the buffer is terminated. As initially written by the host, these registers contain the number of bytes that the buffer can hold. ...
Page 147
... End of Buffer (set by the CD2401 and cleared by the host CPU buffer not complete buffer complete. When the EOB bit is set by the CD2401, the buffer is free for the host to process (RBCNT information is updated to the number of bytes available in the buffer, and a new buffer can be allocated). ...
Page 148
... Bit 13 Bit 7 Bit 6 Bit 5 This register holds the start addresses of the A external buffer used by the CD2401 to transmit the next data block. This register is written by the host and copied internally to control the data transfer from the memory to the CD2401 FIFO. 148 Section 8.5.2.7 on page ...
Page 149
... Bit 13 Bit 7 Bit 6 Bit 5 This register holds the start addresses of the B external buffer used by the CD2401 to transmit the next data block. This register is written by the host and copied internally to control the data transfer from the memory to the CD2401 FIFO. Datasheet Multi-Protocol Communications Controller — CD2401 ...
Page 150
... CD2401 — Multi-Protocol Communications Controller 8.6.5.5 A Buffer Transmit Byte Count (ATBCNT) Register Register Name: ATBCNT Register Description: Transmit Buffer A Byte Count Default Value: x’0000 Access: Word Read/Write Bit 15 Bit 14 Bit 13 Bit 7 Bit 6 Bit 5 8.6.5.6 B Buffer Transmit Byte Count (BTBCNT) Register Register Name: BTBCNT Register Description: Transmit Buffer B Byte Count Default Value: x’ ...
Page 151
... If the CD2401 is to generate and send the CRC for the frame, the FCSApd (COR2[6]) must be set. If the buffer contains the end of a frame, the EOF bit must also be set. When the buffer has been sent, the EOB bit is set by the CD2401, and the 2401own bit is reset allowing a new buffer to be allocated. ...
Page 152
... CD2401 — Multi-Protocol Communications Controller EOB bit. When the host completes use of the buffer, it must issue the append complete command through STCR. The CD2401, upon transmitting the last characters from the buffer, sets EOB, thus allowing the host to allocate a new transmit buffer. ...
Page 153
... Register Description: Receive Timeout Period – low byte Default Value: x’00 Access: Byte Read/Write – Async mode only Bit 7 Bit 6 Bit 5 Datasheet Multi-Protocol Communications Controller — CD2401 Bit 4 Bit 3 Bit 2 Binary Value 2048. The timer prescaler establishes the clock for the Async Mode only – ...
Page 154
... CD2401 — Multi-Protocol Communications Controller 8.7.2.2 Receive Timeout Period Register – High (RTPRh) – Async Mode only Register Name: RTPRh Register Description: Receive Timeout Period – high byte Default Value: x’00 Access: Byte Read/Write – Async mode only Bit 7 Bit 6 RxEn RxFloff RxFlon The value in this register sets the receive data timeout period in Async mode ...
Page 155
... Interrupt Status register and a reload timer command in the End of Interrupt register for the interrupt being serviced single-interrupt routine, only one general timer can be restarted this way. Datasheet Multi-Protocol Communications Controller — CD2401 Bit 12 Bit 11 Bit 10 Binary Value ...
Page 156
... Default Value: x’00 Access: Byte Read only Bit 7 Bit 6 Bit 5 This Asynchronous mode timer is managed by the CD2401 to implement embedded transmit delays when that option is used by the host (see description of COR2). This register should not be modified by the host under any circumstances. 156 Bit 4 ...
Page 157
... Note: The maximum CLK of 35 MHz applies to Revision M and later devices only; Revisions K and L remain specified at 33 MHz maximum, revisions prior to K remain specified at 20 MHz maximum. All values in the following tables apply to the 35-MHz specification. Datasheet Multi-Protocol Communications Controller — CD2401 ) 0.5 V (volts ...
Page 158
... CD2401 — Multi-Protocol Communications Controller 9.3 AC Electrical Characteristics Symbol t Period of CLK input (35 MHz maximum) PERIOD t CLK high to BUSCLK high 1 t CLK high to BUSCLK low 2 Bus Arbitration t CLK high to BGACK* tristate 11 t BGIN* low to address valid 12 t Address hold after CLK high 13 t CLK high to address tristate ...
Page 159
... Figure 17. CLK/BUSCLK/RESET* Timing Relationship t PERIOD CLK BUSCLK RESET* During RESET* active period, BUSCLK is held low. BUSCLK will transition high and begin running at one/half CLK frequency on the first rising edge of CLK after RESET* is released. Datasheet Multi-Protocol Communications Controller — CD2401 Parameter MIN MAX 5 ...
Page 160
... CD2401 — Multi-Protocol Communications Controller Figure 18. Slave Read Cycle Timing CLK BUSCLK t 41 DS A[7:0] A/D[15:0] DTACK DATEN* /DATDIR* 160 Datasheet ...
Page 161
... Figure 19. Slave Write Cycle Timing CLK BUSCLK t 41 DS A[7:0] A/D[15:0] DTACK DATEN* Datasheet Multi-Protocol Communications Controller — CD2401 161 ...
Page 162
... CD2401 — Multi-Protocol Communications Controller Figure 20. Interrupt Acknowledge Cycle Timing CLK BUSCLK t 61 DS A[7:0] A/D[15:0] DTACK DATEN*/DATDIR* 162 Datasheet ...
Page 163
... Figure 21. Bus Arbitration Cycle Timing CLK BUSCLK BR* BGIN* ADLD* A[7:0] A/D[15:0] AS* AEN*/DATEN*/ DATDIR* BGACK* R/W* NOTE: In DMA Read cycle, these pins will be tristate; in DMA Write cycle, these pins will be D[15:0]. Datasheet Multi-Protocol Communications Controller — CD2401 A[15:8] A[31:16 A[7:0] NOTE ...
Page 164
... CD2401 — Multi-Protocol Communications Controller Figure 22. Bus Release Timing CLK BUSCLK AS*, DS* A[7:0] A/D[15:0] BGACK* R/W* AEN*/DATEN*/ DATDIR* 164 Datasheet ...
Page 165
... Figure 23. DMA Read Cycle Timing CLK BUSCLK A[7:0] A/D[15:0] DTACK* BERR* Datasheet Multi-Protocol Communications Controller — CD2401 BERR* Timing setup time to CLK rising edge = hold time after CLK rising edge = 20 ns ...
Page 166
... CD2401 — Multi-Protocol Communications Controller Figure 24. DMA Write Cycle Timing CLK BUSCLK t 24 AS* DS A[7: A/D[15:0] DTACK* BERR* 166 BERR* Timing setup time to CLK rising edge = hold time after CLK rising edge = ...
Page 167
... Revision I or older are available in the EIAJ package; Revision M and newer are available in the JEDEC package. 2. Dimensions are in millimeters (inches), and controlling dimension is millimeter. 3. Before beginning any new design with this device, please contact Intel for the latest package information. Datasheet Multi-Protocol Communications Controller — CD2401 22.95 (0.904) 23.45 (0.923) 19.90 (0.783) 20.10 (0.791) ...
Page 168
... CD2401 — Multi-Protocol Communications Controller 11.0 Ordering Information Example Communications, Data † Contact Intel Corporation for up-to-date information on revisions. 168 SCD240110QCM Product line: Part number Internal reference number † Revision Temperature range Commercial Package type: MQFP (metric quad flat pack) Datasheet ...
Page 169
Index A abbreviations 13 absolute maximum ratings 157 AC electrical characteristics bus arbitration 158 DMA read 158 DMA write 158 host read/write 158 interrupt acknowledge 159 acronyms 14 Addressing mode 94 Append mode 56 Async-HDLC/PPP mode 31, 102, 119, 122, ...
Page 170
... Idle mode 100 interrupt acknowledge 159 interrupts acknowledge cycle 39 contexts and channels 38 groups and types 39 IACK cycles 41 keep and pass logic 42 multi–CD2401 systems 42 registers 38 systems with interrupt controllers 42 transmit and receive interrupt service re- quests 41 K keep and pass logic 42 L Local Loopback mode 115 ...
Page 171
R read cycle, host 36 receive buffer interrupts 56 receive bus errors 57 receive DMA transfer 51 receive FIFO operation 43 receive timeout 57 Receive Transfer mode 93 receiver A and B buffers 51 register definitions 26 register table 21 ...
Page 172
REOIR 23, 31, 134 RFOC 23, 31, 133 RIR 23, 30, 128 RISR 23, 31, 129 RISRh 23, 31, 132 RISRl 23, 31, 129 RPILR 23, 30, 127 Timer registers GT1 26, 34, 154 GT1h 26, 34, 155 GT1l 26, ...
Page 173
Bit Index 146 150 2401own , A 119 AbortTx 94 AdMde[1:0] 94 AFLO 100 Alt1 119 AppdCmp 142 150 Append , B 132 136 BA/ BCC 132 136 146 150 Berr , , , 143 147 152 Binary ...
Page 174
InitCh 106 INLCF 106 INPCK 150 INTR 108 IStrip 124 IT[1:0] 96 IXM L 131 LChg 115 LLM 108 LNE 98 LRC 131 LVal M 139 Mact 139 Mcn[1:0] 125 Mdm 139 Men 139 Meo 126 MLvl[1:0] 139 Mvct[1:0] ...
Page 175
Tvct[1:0] 137 TxCt[4:0] 125 TxD 136 TxDat 136 TxEmpty 120 121 122 154 TxEn , , , 120 TxFlag 121 154 TxFloff , 121 154 TxFlon , 120 122 TxFrame , 96 TxIBE 122 TxITB 120 TxMark 93 TxMode ...
Page 176
...