CD2401 Intel, CD2401 Datasheet - Page 103

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

Datasheet
Register Name: COR3
Register Description: Channel Option 3
Default Value: x’00
Access: Byte Read/Write
SglSYN
Bit 7
Note: The SglSYN option is only available for Extended X.21 mode; standard X.21 mode always
Note: This option is not available in revisions prior to Revision ‘H’.
COR3 — X.21 Mode
Bit 7
requires two SYN characters. When the SglSYN option is set, StpSYN and SCDE options are
disabled.
Bit 6
SSDE
Bit 6
Single SYN
This bit determines the number of SYN characters that need to be received before
Character Synchronization mode is considered received.
0 = two SYN characters are required.
1 = one SYN character is required.
Steady State Detect Enable
When set, this bit enables the checking of special receive conditions relevant to
X.21. These conditions are:
To be detected as a special condition, a change must be present for at least 16-bit
times. When detected, a receive exception interrupt is generated with the relevant
status set in the RISR. After detection of the special condition, no further data is
passed to the host until different data is received.
1. All ‘0’s
2. All ‘1’s
3. Alternating ‘0’s and ‘1’s.
4. Change in the condition of the CTS* pin (CTS* is used as the ‘I’ lead for DTE,
StrpSYN
0
0
0
Bit 5
or the ‘C’ lead for DCE).
pad2
0
1
1
0
0
1
SCDE
Bit 4
through
Multi-Protocol Communications Controller — CD2401
pad1
1
0
1
Bit 3
0
1
0
0
pad0
1
1
1
Bit 2
0
Number of Leading Pads
Reserved – do not use.
Motorola Hex Address: x’16
Bit 1
Intel Hex Address: x’15
0
0
1
2
3
Bit 0
0
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