CD2401 Intel, CD2401 Datasheet - Page 37

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

5.1.2
5.2
Datasheet
Figure 3. Host Write Cycle
A[7:0], SIZ[1:0]
A/D[15:0]
Byte and Word Transfers
Data can be moved to and from the CD2401 in either byte or word transfers. To accommodate
various families of host processors, the BYTESWAP input pin is set to indicate the system byte-
ordering scheme. SIZ[1:0] indicate whether the transfer is 1 or 2 bytes wide.
In systems where the even addresses represent the high-order byte, the BYTESWAP input pin
should be tied low, and byte transfers occur on the A/D[15:8] pins for even addresses and on the A/
D[7:0] pins for odd addresses. In systems where the high-order byte is on the odd address, the
situation is reversed, and BYTESWAP should be tied high. Byte transfers to even addresses occur
on the A/D[7:0] pins, and to odd addresses on the A/D[15:8] pins.
Interrupts
The CD2401 uses interrupt requests to alert the host that certain events have occurred. Interrupt
operations on the CD2401 are tightly coupled with several registers described below. The concept
of context affects the accessibility of these and other registers.
DATDIR*
DTACK*
DATEN*
R/W*
CS*
DS*
Multi-Protocol Communications Controller — CD2401
DIN
37