WM8501 Wolfson Microelectronics plc, WM8501 Datasheet - Page 12

• Manufacturer Part Number: WM8501
• Description: 24-bit 192khz Stereo Dac With 1.7vrms Line Driver
• Manufacturer: Wolfson Microelectronics plc

WM8501
AUDIO DATA SAMPLING RATES
HARDWARE CONTROL MODES
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Figure 6 DSP Mode B Timing
The master clock for WM8501 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8501 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCLK, although the WM8501 is tolerant of phase
differences or jitter on this clock.
Table 1 Master Clock Frequencies Versus Sampling Rate
The WM8501 is hardware programmable providing the user with options to select input audio data
format, de-emphasis and mute.
ENABLE OPERATION
Pin 4 (ENABLE) controls the operation of the chip. If ENABLE is low the device is held in a low
power state. If this pin is held high the device is powered up.
To ensure correct operation it is essential that there is a low to high transition on the ENABLE pin
after digital supplies have come on. This can be achieved by providing the ENABLE signal from
an external controller chip or by means of a simple RC network on the ENABLE pin. See
“Recommended External Components” in the “Application Information” section at the end of this
datasheet.
Note that the ENABLE pin should not be used as a mute pin or to temporarily silence the DAC
(between tracks of a CD for example). The ENABLE pin is not intended to be used as a mute
control but to allow entry into low power mode. Disabling the device via the ENABLE pin has the
effect of powering down the voltage on the VMID pin. Repeated enabling/disabling of the device
can cause audible pops at the output.
SAMPLING
LRCLK
(LRCLK)
BCLK
44.1kHz
192kHz
DIN
32kHz
48kHz
96kHz
RATE
MSB
1
Input Word Length (16 bits)
Max 4 BCLK's
LEFT CHANNEL
2
5.6448
24.576
12.288
4.096
6.144
128fs
15
LSB
16
1
18.432
36.864
6.144
8.467
9.216
192fs
MASTER CLOCK FREQUENCY (MHz) (MCLK)
RIGHT CHANNEL
2
Unavailable
15
11.2896
12.288
24.576
8.192
256fs
16
1/fs
Unavailable
16.9344
12.288
18.432
36.864
384fs
NO VALID DATA
Unavailable
Unavailable
22.5792
16.384
24.576
512fs
PD, Rev 4.2, July 2009
Production Data
Unavailable
Unavailable
33.8688
24.576
36.864
768fs
1
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