EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet
EVX10AS150ATP
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EVX10AS150ATP Summary of contents
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Datasheet Features • ADC 10-bit Resolution • 2.5 Gsps Sampling Rate • Selectable 1:4 or 1:2 Demultiplexed Digital LVDS Outputs • True Single Core Architecture (No Calibration Required) • External Interleaving Possible Via 3-Wire Serial Interface – Gain ...
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EV10AS150A Applications • Direct Broadband RF Down Conversion • Wide Band Communications Receiver • High Speed Instrumentation • High Speed Data Acquisition Systems 1. Block Diagram The EV10AS150A combines a 10-bit 2.5 Gsps fully bipolar analog-to-digital converter chip, driving a ...
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Specifications This section describes the device specifications in terms of: • Absolute max ratings • Recommended conditions of use • Electrical operating characteristics • Timings 2.1 Absolute Maximum Ratings Absolute maximum ratings are limiting values (referenced to GND = ...
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EV10AS150A Table 2-1. Absolute Maximum Ratings (Continued) Parameter ADC Reset Voltage DMUX function input voltage DMUX Asynchronous Reset DMUX Control Voltage Maximum input voltage on DIODE Maximum input current on DIODE Max Junction Temperature Storage temperature ESD protection (HBM) Notes: ...
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Analog Input Max Ratings in Single Ended Configuration Internal DC common mode bias for differential analog inputs is +3V. Input impedance on V Max rating is ±1V on one single ended signal, corresponding to 2 Vpp on 50Ω Limiting ...
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EV10AS150A 2.2 Recommended Conditions of Use Table 2-2. Recommended Conditions of Use Parameter Power supplies Analog 3.3V Power Supply voltage Analog 5.0V Power Supply voltage Digital 3.3V Power Supply voltage Output 2.5V Power Supply voltage Analog Input Recommended Configuration Clock ...
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Electrical Characteristics for Supplies, Inputs and Outputs Unless otherwise specified: Values are given over temperature and power supplies range. Table 2-4. Electrical Characteristics for Supplies, Inputs and Outputs Parameter Power requirements Power Supply voltages Analog 5.0V Analog 3.3V Digital ...
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EV10AS150A Table 2-4. Electrical Characteristics for Supplies, Inputs and Outputs (Continued) Parameter Input resistance - Single-ended - Differential Clock inputs Logic common mode compatibility for clock inputs (1) ADC intrinsic clock jitter Clock inputs internal DC common mode voltage Clock ...
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Table 2-4. Electrical Characteristics for Supplies, Inputs and Outputs (Continued) Parameter RS, BIST, STAGG, SLEEP, DRTYPE (Control Input Voltages) (3) - Logic low Resistor to ground Voltage level Input low current (3) - Logic high Resistor to ground Voltage level ...
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EV10AS150A 2. ADC gain with programmed default value. This ADC Gain can be fine tuned to “1” by monitoring of the gain adjust function through the 3WSI serial interface. 3. ADC offset with programmed default values. The ADC Offset can ...
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Table 2-7. Dynamic Converter Characteristics with Differential Analog Input (Continued) Parameter Total Harmonic Distortion (10 harmonics 2.5 Gsps Fin = 500 MHz Fs = 2.5 Gsps Fin = 1245 MHz Fs = 2.5 Gsps Fin = 2495 MHz ...
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EV10AS150A Table 2-7. Dynamic Converter Characteristics with Differential Analog Input (Continued) Parameter Ain = –13 dBFS, Differential or single ended analog input, +1 dBm differential clock (1 Vpp in 100Ω), 50% external duty cycle, Binary output mode Signal to Noise ...
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Table 2-8. Dynamic Converter Characteristics with Single Ended Analog Input (Continued) Parameter Spurious Free Dynamic Range Fs = 2.5 Gsps Fin = 500 MHz Fs = 2.5 Gsps Fin = 1245 MHz Fs = 2.5 Gsps Fin = 2495 MHz ...
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EV10AS150A Table 2-10. Switching characteristics (Continued) Parameter Minimum Clock pulse width (High) Minimum Clock pulse width (Low) (1) External clock Duty cycle (2) Aperture Delay (2) Aperture Jitter added by the ADC Output Rise/Fall time for Data (20% – 80%) ...
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A • 6.5 clock cycles for port B • 5.5 clock cycles for port C • 4.5 clock cycles for port D In simultaneous output mode with 1:2 DMUX ratio, the latency becomes respectively ...
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EV10AS150A In staggered mode, the differential delays are (TOD1-TDR1), (TOD2-TDR2), (TOD3-TDR3), (TOD4- TDR4). See Figure 2-4 on page Therefore the absolute delay values TOD and TDR are not actually of interest: only the time difference TOD-TDR has to be actually ...
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The order of magnitude of time difference TD1-TD2 is identical to TOD-TDR: Except that TOD-TDR is frequency independent, whereas TD1 and TD2 are sampling frequency depen- dent: For example at 1:4 DMUX ratio, the data pulse width at maximum operating ...
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EV10AS150A Figure 2-3. Timing Diagram Simultaneous mode, 1:4 DMUX Ratio VIN ADC CLK Digital Outputs ADC ( internal ) ADC Data Clock ( internal Fclock/2) DMUX Even Latches DMUX Odd Latches Port Select A Port Select B Port Select C ...
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Figure 2-4. Timing Diagram Staggered mode, 1:4 DMUX Ratio VIN ADC CLK ADC Digital ADC Outputs ADC Data Clock (Fclock / 2) DMUX Even Latches DMUX Odd Latches ADC Fclock / 4 Port Select A Port Select B DMUX Port ...
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EV10AS150A 2.7 Digital Output Data Coding Table 2-11. Digital Output Data Coding Table Differential analog input Voltage level > 250.25 mV >Top end of full scale + ½ LSB 250.25 mV Top end of full scale + ½ LSB 249.75 ...
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Definition of Terms Maximum Sampling (Fs max) Frequency Minimum Sampling (Fs min) frequency (BER) Bit Error Rate Full power input (FPBW) bandwidth Small Signal Input (SSBW) bandwidth Signal to noise and (SINAD) distortion ratio (SNR) Signal to noise ratio ...
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EV10AS150A 2.9 Definition of Terms (Continued) The difference TD1-TD2 gives an information if the output clock is centered on the output data. If output TD1-TD2 clock is in the middle of the data TD1 = TD2 = Tdata/2. TC1 = ...
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Pin Description 3.1 Pinout View Figure 3-1. EBGA 317 Pinout Table (View from Bottom of the Package) Note: Area in dashed line corresponds to dam & fill (note an exposed pad) e2v semiconductors SAS 2009 EV10AS150A 23 0954B–BDC–12/09 ...
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EV10AS150A 3.2 Pin Description Table Table 3-1. Pin Description Table Signal Name Pin Number POWER SUPPLIES A24, A26, A27, B24, B26, B27, C24, C26, C27, V D24, D26, D27, CCA5 E24, E26, F25, L25, L26, M27, R21, T21, U21 A25, ...
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Table 3-1. Pin Description Table (Continued) Signal Name Pin Number B21, B23, C21, C23, D21, D23, E21, E23, F21, F23, F26, F27, G25, G26, G27, H25, H26, J25, J26, K27, N25, P25, R22, AGND R23, R24, R25, R26, R27, T22, ...
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EV10AS150A Table 3-1. Pin Description Table (Continued) Signal Name Pin Number CLOCK INPUTS CLK W24 CLKN W23 RESET INPUT DRR P27 ASYNCRST B17 26 0954B–BDC–12/09 Description Dir. Equivalent Simplified Schematics VCCAS VCCA3 CLK ADC Clock Differential Inputs CLKN I (On ...
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Table 3-1. Pin Description Table (Continued) Signal Name Pin Number DIGITAL OUTPUTS B16, B15, B14, A0…A9 B13, B12, B11, B10, B9, B8, B7 A16, A15, A14, A0N…A9N A13, A12, A11, A10, A9, A8 AOR/DRAN AORN/DRA A6 B5, B4, ...
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EV10AS150A Table 3-1. Pin Description Table (Continued) Signal Name Pin Number M2, N2, P2, R2, T2, C0…C9 U2, V1, V2, V3, V4 L1, M1, N1, P1, R1, C0N…C9N T1, U1, W2, W3 COR/DRCN CORN/DRC W5 V6, V7, V8, ...
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Table 3-1. Pin Description Table (Continued) Signal Name Pin Number SLEEP A18 STAGG A17 DRTYPE BIST V17 e2v semiconductors SAS 2009 Description Dir. Equivalent Simplified Schematics DMUX SLEEP mode Enable Leave floating or connect ...
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EV10AS150A Table 3-1. Pin Description Table (Continued) Signal Name Pin Number CLKDACTRL U18 CONTROL OUTPUT FUNCTIONS DIODE ADC W21 4. Theory of Operation 4.1 Overview The EV10AS150A is a 10-bit 2.5 Gsps ADC combined with a 1:4 demultiplexer (DMUX) allowing ...
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The main functions of the EV10AS150A ADC are digitally controlled via on-chip DACs controlled by 3- wire serial interface (3WSI): • Sampling Delay Adjust, with a tuning range of ~ 120 ps, with a coarse and a fine tuning available ...
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EV10AS150A 4.2 Functional Pin Table Table 4-1. Functional Pin Table Name V CCA5 V CCA3 V CCD V PLUSD AGND DGND CLK, CLKN INN DRR ASYNCRST DR/DRN A0… A9 A0N…A9N AOR/DRAN, AORN/DRA B0… B9 B0N…B9N BOR/DRBN, ...
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RESETs and ADC Synchronization There are three reset signals available on the device to start the device properly: • DRR (Data Ready Reset) is used to reset and synchronize the Data Ready Output Clock of the ADC. DRR ensures ...
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EV10AS150A Figure 4-1. Asynchronous Reset Timing Diagram, 1:2 Mode, Simultaneous Mode (Principle of Operation) VIN CLK 3.5 ns min DRR ASYNCRST A9…A0 B9…B0 DR (DR mode) DR (DR/2 mode) Figure 4-2. Asynchronous Reset Timing Diagram, 1:4 mode, simultaneous mode (Principle ...
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Control Signal Settings (DMUX) The SLEEP, RS, STAGG, BIST and DRTYPE control signals use the same input buffer. SLEEP, STAGG, BIST are activated on Logic Low (10Ω Grounded), and deactivated on Logic High (10 KΩ to Ground, or tied ...
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EV10AS150A 4.4.1 DMUX Ratio The demultiplexer ratio is programmable thanks to the RS Ratio selection signal. Table 4-3. DMUX Ratio Selection Settings Figure 4-4. DMUX in 1:2 Ratio Figure 4-5. DMUX in 1:4 Ratio 4.4.2 DMUX Data Ready Output Clock ...
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Figure 4-7. DR/2 Mode DR Data Out Table 4-4. DMUX Output Clock Type Selection Settings When DRTYPE is left floating, the default mode is DR. 4.4.3 DMUX Output Data Mode (STAGG) Two output modes are provided: • Staggered: the output ...
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EV10AS150A Figure 4-9. Simultaneous Mode in 1:2 Ratio (STAGG = mode in DR/2 mode Data Out Port A Data Out Port B Figure 4-10. Staggered Mode in 1:2 Ratio (STAGG = 0) Data Out Port A in ...
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Figure 4-11. Staggered Mode in 1:4 Ratio (STAGG = 0) Data Out Port mode in DR/2 mode Data Out Port mode in DR/2 mode Data Out Port mode in DR/2 mode ...
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EV10AS150A 4.4.5 DMUX Power Reduction Mode (SLEEP) The power reduction (SLEEP) mode allows the user to reduce the power consumption of the device (DMUX part in Sleep mode). In this mode, the DMUX part consumption is reduced by 0.9W. The ...
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The output sequence is then: Table 4-5. BIST Output Sequence in 1:4 Mode BIST sequence DATA N on Port A DATA N+1 on Port B DATA N+2 on Port C DATA N+3 on Port D DATA N+4 on Port A ...
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EV10AS150A Please refer to Table 2-4 on page 7 The 3WSI gives a “write-only” access different internal registers bits each. The input format is fixed with always 4 bits of register address ...
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Figure 4-13. 3WSI Timing Diagram RESET SLCK SLDN SDATA Internal Previous setting Register Value Table 4-7. Timings Related to Serial 3 Wire Serial Interface Name Parameter Tsclk Period of SCLK Twsclk High or low time of SCLK Tssldn Setup time ...
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EV10AS150A Table 4-8. 3WSI Settings (Continued) Address Description 0100 Offset Adjust 0110 State Register Notes recommended to adjust clock duty cycle at 35/65% to optimize SFDR and THD at high sampling rate in 2 zone ...
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Sampling Delay Adjust Function (SDA) – ADC Interleaving This function is of most importance for applications based on time interleaving of multiple ADCs, in order to increase the actual sampling rate. In interleaved system the channels relative phasing has ...
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EV10AS150A An accurate tuning of aperture delay, gain and offset allows to interleave two ADCs with minimum num- ber of external analog components, thus providing an equivalent 5 Gsps ADC. Due to matching difficulties of the roll off of the ...
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Figure 4-16. Junction Temperature Versus Diode Voltage for 980 970 960 950 940 930 920 910 900 890 880 870 860 850 840 830 820 810 800 790 780 770 760 750 740 730 720 710 ...
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EV10AS150A Figure 5-1. EV10AS150A Decoupling Schema 5.1.2 Power Supplies Decoupling Schema Figure 5-2. Power Supplies Decoupling Schema 47 nF X3(min X3(min) 5.1.3 Decoupling Capacitors Package Implementation The table below indicates the pins to pins connected together with a ...
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Table 5-1. Decoupling Capacitors Implementation (Continued) Supply V PLUSD V PLUSD V PLUSD V PLUSD V PLUSD V PLUSD V CCD V CCD V CCD V CCD 5.1.4 Decoupling Capacitors PCB Implementation Figure 5-3. Decoupling Capacitors PCB Implementation Evaluation board ...
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EV10AS150A It is important that a digital power plane does not overlap an analog power plane as can be seen on ure 5-4 a). If this constraint is not respected, this will induce capacitance between the overlapping areas, which is ...
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Figure 5-5. Analog and Digital Partitioning of Power and Ground Planes for Optimum Isolation Ground planes Power supplies planes e2v semiconductors SAS 2009 R=0 Ohm High resonant MCM Output buffers ADC + DMUX DGND ADC AGND ADC Digital Analog Ground ...
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EV10AS150A 5.2 Analog Input Implementation 5.2.1 ADC Analog Input Terminations The front-end input preamplifier in on chip terminated (100Ω differential, 50Ω single-ended with accurate thin film TaN resistors with temperature coefficient close to 0°C), driven by 50Ω controlled impedance lines ...
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Since the ADC tolerates degrees of phase unbalance without impacting the dynamic perfor- mance (SFDR not mandatory to use cascaded (double) transformer to improve phase balance characteristics. Double transformer implementations may degrade the inherent band ...
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EV10AS150A However, the THD will be somewhat impacted, since the harmonics are RSS summed since even and odd harmonics have now similar weightings in single-ended: The THD is slightly impacted by – the 1 MHz the ...
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Driving the EV10AS150A with a Sinewave Clock Input The SNR rolloff in the high input frequency region (2 The ADC sampling jitter is 120 fs rms RSS summed with external sampling clock jitter: To achieve optimum SNR ...
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EV10AS150A Maximum operating clock input power shall not exceed + 7 dBm, which corresponds to 2 Vpp on differ- ential 100Ω clock input. This corresponds to slew-rates of 15.7 GV/s Maximum ratings for differential clock input is 3 Vpp which ...
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Integrated double SSB phase noise power in radians (rms): – SQRT(2. compared with 1,86.10 total RSS summed phase noise from 10KHz to 5.5 GHz is: SQRT ((1,86.10 Therefore the close-in phase contribution ...
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EV10AS150A 5.3.2 Driving the EV10AS150A with a Square Wave Differential Cock Input If the clock input signal is a square wave, the incoming signal slew-rate becomes independent to signal amplitude and frequency: So far the slew-rate of the square clock ...
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Note 3: Effect of 3WSI SDA (Sampling Delay Adjust) tunable delay line on ADC intrinsic jitter The previous assumptions are made with ADC intrinsic clock jitter = 120 fs rms, which is assuming the sampling clock adjust is de-activated (SDA ...
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EV10AS150A Figure 5-7. Differential Digital Outputs Terminations (100Ω LVDS) EV10AS150A Output Data Differential Output 5.5 DRR and ASYNCRST Implementation 50Ω termination of reset drivers need to be placed as close as possible of EV10AS150A ADC. Figure 5-8. DRR and ASYNCRST ...
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Package Description 6.1 Package Outline Figure 6-1. EBGA 317 Package Outline Corner E Ni Plated TOP VIEW DETAIL A SIDE VIEW A2 A4 ddd C DETAIL A 5 e2v semiconductors SAS 2009 ...
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EV10AS150A 6.2 Land Pattern Recommendation Figure 6-2. EBGA 317 Land Pattern Recommendation 25.00 62 0954B–BDC–12/09 TOP VIEW B BOTTOM VIEW ...
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Thermal Characteristics As there is no JEDEC standard definition for the thermal resistance applied to a multi-die device, only the thermal resistance for each die (ADC block powered ON only or DMUX block powered ON only) is provided. All ...
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... Commercial grade Standard 0°C < < 90°C amb J Industrial grade Standard –40°C < < 110°C amb J Ambient Prototype Comments Production version Production version Production version Production version Evaluation Board with soldered EVX10AS150ATP prototype in EBGA317 package e2v semiconductors SAS 2009 ...
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Table of Contents Features ..................................................................................................................... 1 Performance ................................................................................................ 1 Screening..................................................................................................... 1 Applications................................................................................................. 2 1 Block Diagram ............................................................................................ 2 2 Specifications ............................................................................................. 3 2.1 Absolute Maximum Ratings ..................................................................................... 3 2.2 Recommended Conditions of Use ........................................................................... 6 2.3 Electrical Characteristics for Supplies, ...
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Package Description ................................................................................ 61 6.1 Package Outline .................................................................................................... 61 6.2 Land Pattern Recommendation ............................................................................. 62 6.3 Thermal Characteristics ......................................................................................... 63 6.4 Moisture Characteristics ........................................................................................ 64 7 Ordering Information ............................................................................... 64 Table of Contents......................................................................................... i ii 0954B–BDC–12/09 EV10AS150A e2v semiconductors ...
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How to reach us Home page: www.e2v.com Sales offices: Europe Regional sales office e2v ltd 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel: +44 (0)1245 493493 Fax: +44 (0)1245 492492 mailto: enquiries@e2v.com e2v sas 16 Burospace F-91572 Bièvres Cedex ...
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EV10AS150A e2v semiconductors SAS 2009 ...