EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 15

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

2.6.3
2.6.4
e2v semiconductors SAS 2009
Data Ready Positioning Versus Output Data (DR/2 Mode and DR Mode)
Differential Timing Values TOD-TDR Versus Absolute Timing Values TOD and TDR
In simultaneous output mode with 1:2 DMUX ratio, the latency becomes respectively 5.5 and 4.5 Clock
cycles on port A and port B, with same TOD propagation delay.
In staggered output mode, the latency of the 4 Digital output ports A,B,C,D is the same, since data are
presented on output port as soon as available.
In staggered mode for 1:4 DMUX ratio and 1:2 DMUX ratio latency is only 4.5 Clock cycles for port A, B,
C and D (see Timing Diagram).
The output propagation delays TOD1, TOD2, TOD3, and TOD4 of the 4 outputs ports in staggered mode
can be considered as identical to TOD.
The Data Ready output clock signal (DR, DRN) is synchronized with ADC (CLK, CLKN) differential clock
falling edges to be synchronous with Digital output data (since digital data are output on falling edge of
sampling Clock after a latency of 7.5 Clock cycles).
In 1:4 DMUX Ratio, the (DR, DRN) signal is shifted by 2 clock cycles in order to be located at center of
data pulse.
In 1:2 DMUX Ratio, the (DR, DRN) signal is shifted by 1 clock cycle to be located at center of data pulse.
Furthermore, the output propagation delay (TDR) of the Data Ready signal and the output propagation
delay of the digital data (TOD) are matching very closely, and track each other over full operating tem-
perature range.
Therefore the Data signals and Data clock signals are synchronized at Package output, with the differen-
tial Data Ready output clock pulse rising edge being centered within Data pulse, in either dual Data rate
mode (DR/2) or DR mode.
In dual data rate (DR/2 mode), the Data clock switches at the same rate as the digital data, and therefore
both the rising and falling edges of (DR, DRN) data clock are located at the center of the data pulse over
temperature (with max TOD-TDR = 100 ps).
In DR mode, the Data clock switches at twice the rate of the digital data, with the differential Data Ready
pulse rising edge being centered within Data pulse and differential falling edges being synchronous with
Data transitions.
The absolute values for TOD and TDR are given for information only, and are corresponding to the digi-
tal output data propagation delay and to the Data Ready output propagation delay, related to ADC output
buffers throughput delay and package propagation times.
TOD and TDR are measured at Package I/Os level, (Input/Outputs Balls), taking out the board extra
propagation delays of the 50Ω/100Ω controlled impedance lines.
Assuming the application board trace lengths are matched for digital data and data ready lines (within
skew limit), one has only to consider the time difference between differential digital data outputs and dif-
ferential Data clock signals TOD-TDR in simultaneous mode.
• 7.5 clock cycles for port A
• 6.5 clock cycles for port B
• 5.5 clock cycles for port C
• 4.5 clock cycles for port D
EV10AS150A
0954B–BDC–12/09
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