EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 31

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EVX10AS150ATP

Manufacturer Part Number
EVX10AS150ATP
Description
Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
Manufacturer
ETC-unknow
Datasheet

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Part Number
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Part Number:
EVX10AS150ATP
Manufacturer:
E2V
Quantity:
20 000
e2v semiconductors SAS 2009
The main functions of the EV10AS150A ADC are digitally controlled via on-chip DACs controlled by 3-
wire serial interface (3WSI):
The Sampling Delay Adjust function (controlled through the 3WSI) may be used to fine-tune the ADC
aperture delay from 0 to 120 ps. The SDA function is very useful when interleaving multiple ADCs.
The output demultiplexing ratio 1:4 or 1:2 can be selected by the means of RS digital control input.
The data outputs are available at the output of the EV10AS150A with two different latency modes:
A Built-In Test (BIST) is provided for quick debug or acquisition setup: activation of checker board like
pattern generator.
The ADC junction temperature monitoring is made possible through the DIODE ADC input by sensing
the voltage drop across a diode implemented on the ADC close to chip hot point.
The EV10AS150A is delivered in an Enhanced Ball Grid Array (EBGA), suitable for applications sub-
jected to large thermal variations (thanks to its TCE which is similar to FR4 material TCE).
• Sampling Delay Adjust, with a tuning range of ~ 120 ps, with a coarse and a fine tuning available (8-
• Offset Control, ± 20 mV, 8-bit resolution.
• Gain Control, ±0.5 dB, 8-bit resolution
• Delay adjustment between the logical clock and the T/H clock, 0 to 30 ps (5-bit resolution).
• Internal clock duty cycle adjust from 60% to 70% at 2.5 Gsps (5-bit resolution).
• Selectable Binary or the Gray coding mode.
• Selectable inversion of MSB for Binary two's complement.
• Reset to program quickly all registers to default values.
• NAP (ADC part) mode to save power when device is not used.
• Staggered (Low latency): data output on ports A, B, C and D are shifted from one clock cycle
• Simultaneous: data output on all ports A, B, C and D are aligned.
bit resolution on the fine tuning of ~30 ps);
between two successive ports.
EV10AS150A
0954B–BDC–12/09
31

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