EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 52

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
5.2
5.2.1
52
Analog Input Implementation
0954B–BDC–12/09
ADC Analog Input Terminations
The front-end input preamplifier in on chip terminated (100Ω differential, 50Ω single-ended with accurate
thin film TaN resistors with temperature coefficient close to 0°C), driven by 50Ω controlled impedance
lines (100 Ω differential) with the multilayer EBGA317 Package.
This allows flat input Voltage Standing Wave Ratio (VSWR) over frequency, (< 1.25:1 measured for
packaged ADC, from DC up to 3 GHz (less than 1.3% of incoming power reflected from the ADC input, <
0.05 dB transmission loss), and < 1.5:1 from 3 GHz to 5 GHz Full power input bandwidth of the ADC
(less than 4% of power reflected from ADC input, < 0.17 dB transmission loss).
The low input VSWR together with the 5 GHz (–3 dB) full power input Bandwidth of the ADC, allows
operation up to the 3
ations related to packaged ADC input impedance deviation from ideal Z = 50Ω (including package
parasitics).
The on-chip terminations (in-phase V
resistive voltage splitter of 55Ω + 550Ω biased under +3.3V to ground, providing proper 50Ω termination
(550 // 55 = 50), together with 3V internal DC common mode biasing. Since the internal analog input DC
common mode is +3V, the differential Analog inputs shall be driven through high resonant (> 5 GHz) DC
blocking capacitors.
Driving the EV10AS150A in single-ended for ADC Full Scale voltage span:
If single-ended driven, the applied in-phase (V
is 0.5V peak-to-peak, (i.e. –2 dBm Full Scale input power into 50Ω on-chip termination.)
For proper symmetric input impedance matching, the inverted phase input (V
minated by 50Ω to Ground through a DC blocking chip capacitor. The inverted phase (V
on-chip 50Ω terminated and biased the same way as the in-phase analogue input.
Driving the EV10AS150A in differential for ADC Full Scale voltage span:
If entered in differential, each analog input (in-phase V
±0.125V peak = 0.25V peak-to-peak amplitude, to comply with 0.5V ADC Full Scale voltage span.
Since the 0.5Vpp Full Scale input voltage span is applied onto 100Ω termination instead of 50Ω, the
ADC Full Scale differential input power into 100Ω loading is –5 dBm instead of –2 dBm into 50Ω if single-
ended driven.
Low cost low profile sub-miniature unbalanced to balanced transformers (baluns) are commercially avail-
able, designed specifically for driving differential inputs and/or output locations for fast sampling ADCs in
the GHz range. These baluns are providing 50Ω impedance on unbalanced input, and 100Ω impedance
on the balanced differential output port, making it easy to use on surface mount application boards to
drive AC coupled differential Analog inputs and clock inputs.
For optimum SFDR performance, the maximum phase balance shall not exceed 12 degree and less
than 1.5 dB for amplitude balance, over the entire band of operation. For example, for operation over the
2
Balance within a band of operation of 1.6 GHz to 3 GHz are available (for roughly 1 dB insertion loss).
Baluns covering a larger band of operation (e.g. 400 MHz to 3000 MHz) with 12 degrees max Phase
unbalance and 1.5 dB Amplitude Balance are also convenient.
nd
Nyquist region at 2.5 Gsps, baluns featuring less than 6 degree Phase Balance and 1 dB amplitude
rd
Nyquist region (including L_Band and S_Band) with negligible carrier level fluctu-
I N
IN
and inverted phase V
) input voltage amplitude for ADC full-scale voltage span
IN
and inverted phase V
I N N
) are actually based on a
INN
INN
e2v semiconductors SAS 2009
) must be externally ter-
) shall be entered with
INN
) is internally