EM65568 ELAN Microelectronics Corp, EM65568 Datasheet - Page 74

• Manufacturer Part Number: EM65568
• Description: 130 Com/ 128 Seg 4096 Color Stn Lcd Driver
• Manufacturer: ELAN Microelectronics Corp

In each operation mode, the following increment operation is performed:
(i)
(ii)
8.2.8 Power Control Register
(At the tine of reset: {AMPON, HALT,DCON,ACL}=0H, read address: BH)
ACL
The internal circuit can be initialized. This register is effective only at Master operation mode.
ACL = “0”: Normal operation
ACL = “1”: Initialization ON
When the reset operation begins internally after ACL register sets to “1”, the ACL register is automatically cleared to “0”. The
internal reset signal has been generated with a clock (built-in oscillation circuit or CK input) for the display. Therefore, install
the WAIT period for the display clock two cycles at least. After WAIT period, next operation can handle. Since built-in
oscillation circuit and external CK input can not be used in the slave mode, the setting of the ACL register becomes the
invalidity. Certainly use the RESB terminal, when the reset is applied on the slave chip.
DCON
The internal booster circuit is set ON/OFF
DCON = “0”: Booster circuit OFF
DCON=”1”: Booster circuit ON
HALT
The conditions of power saving are set ON/OFF by this command.
HALT = “0”: Normal operation
HALT=”1”: Power-saving operation
When setting in the power-saving state, the consumed current can be reduced to a value near to the standby current.
The internal condition at power saving are as follows.
(a)
(b)
(c)
* This specification is subject to be changed without notice.
D7
1
Address are incremented as described above.
Two bytes are accessed by accessing the RAM once.
The X-addresses increment in the order of 00H,01H,…3EH,and 3FH.
D6
When gradation display mode and 8-bit access are selected
When gradation display mode and 16-bit access are selected:
0
The oscillating circuit and power supply circuit are stopped.
The LCD drive is stopped, and output of the segment driver and common driver are VSS level.
The clock input from CK pin is inhibited.
D5
1
D4
1
AMPON HALT DCON ACL
D3
D2
D1
D0
130 COM/ 128 SEG 4096 Color STN LCD Driver
74
CSB
0
RS
1
RDB WRB RE2 RE1 RE0
1
0
0
0
0
2005/3/8 (V1.2)
EM65568