ADRF6750 Analog Devices, Inc., ADRF6750 Datasheet
ADRF6750
Related parts for ADRF6750
ADRF6750 Summary of contents
Page 1
... MHz to 1575 MHz for use in satellite, cellular and broadband communications. The ADRF6750 modulator includes a high modulus fractional-N frequency synthesizer with integrated VCO, providing better than 1 Hz frequency resolution, and digitally controlled output attenuator with 1 dB steps. ...
Page 2
... ADRF6750 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 18 Overview ...................................................................................... 18 PLL Synthesizer and VCO ......................................................... 18 Quadrature Modulator .............................................................. 20 Attenuator .................................................................................... 21 Voltage Regulator ....................................................................... 21 EXTERNAL vco OPERATION ................................................ 21 REVISION HISTORY 1/10— ...
Page 3
... Maximum frequency error = 100 Hz Maximum Frequency Step for Frequency step with no autocalibration routine; No Autocalibration Register CR24, Bit Phase Detector Frequency = 0.9 V p-p differential = 3.5 MHz 4.5 MHz −6 dBm per tone BB OUT Rev Page ADRF6750 Min Typ Max Unit 950 1575 MHz −1.6 dBm ±0.5 dB 8.5 ...
Page 4
... ADRF6750 Parameter Test Conditions/Comments GAIN CONTROL Gain Range Step Size Relative Step Accuracy Fixed frequency, adjacent steps All attenuation steps Over full frequency range, adjacent steps 2 Absolute Step Accuracy 47 dB attenuation step Output Settling Time Any step; output power settled to ±0.2 dB ...
Page 5
... VD;DAT t 900 VD;ACK t 1300 BUF t VD;DAT AND t t SU;DAT VD;ACK (ACK SIGNAL ONLY) t SU;STA t HIGH 2 Figure Port Timing Diagram Rev Page ADRF6750 Unit kHz max ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min t BUF t SU;STO STOP ...
Page 6
... ADRF6750 SPI Interface Timing Table 3. 1 Parameter Symbol CLK Frequency f CLK CLK Pulse Width High t CLK Pulse Width Low t Start Condition Hold Time t Data Setup Time t Data Hold Time t Stop Condition Setup Time t SDO Access Time SDO High Impedance t 1 See Figure 3. ...
Page 7
... Exposure to absolute 2.5 V maximum rating conditions for extended periods may affect −0 device reliability. −0 ESD CAUTION 1.5 V 26°C/W 120°C −65°C to +150°C Rev Page ADRF6750 ...
Page 8
... CCOMP1 to CCOMP3 38 VTUNE 7 RSET 9 CP VCC4 1 PIN 1 IBBP 2 INDICATOR IBBN 3 QBBN 4 QBBP 5 AGND 6 ADRF6750 RSET 7 LF3 8 TOP VIEW CP 9 (Not to Scale) LF2 10 VCC1 11 REGOUT 12 VREG1 13 VREG2 14 NOTES 1. CONNECT EXPOSED PAD TO GROUND PLANE VIA A LOW IMPEDANCE PATH. Figure 4. Pin Configuration Description Positive Power Supplies for I/Q Modulator ...
Page 9
... Muxout. This output is a test output for diagnostic use only. It should be left unconnected by the customer. Exposed Paddle. Connect to ground plane via a low impedance path. Rev Page ADRF6750 2 C Port. In SPI mode, this pin is a high 2 C mode, this pin is a bidirec- ...
Page 10
... ADRF6750 TYPICAL PERFORMANCE CHARACTERISTICS 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, REFIN = 10 MHz, PFD = 20 MHz baseband frequency = 1 MHz, LOMONx is off, unless otherwise noted. A nominal condition is defined as 25°C, 5.00 V, and worst-case frequency. A worst-case condition is defined as having the worst-case temperature, supply voltage, and frequency. ...
Page 11
... Figure 16. Output IP3 Distribution at Nominal and Worst-Case Rev Page NOMINAL 45 WORST-CASE 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 OUTPUT P1dB (dBm) and Worst-Case Conditions LO FREQUENCY (MHz) Nominal Conditions 45 NOMINAL 40 WORST-CASE OUTPUT IP3 (dBm) Conditions ADRF6750 8.8 9.0 9.2 ...
Page 12
... ADRF6750 OUTPUT IP3 INTERCEPT POINT (dBm) Figure 17. Output IP3 vs. LO Frequency at Nominal Conditions –60 –70 –80 ATTENUATION = 0dB –90 –100 –110 –120 –130 ATTENUATION = 47dB –140 LO FREQUENCY (MHz) Figure 18. LO Off Isolation vs. Attenuation, LO Frequency, Supply, and Temperature – ...
Page 13
... THIRD –120 HARMONIC –130 –140 –150 –160 100 Figure 28. Phase Noise Performance vs. LO Frequency, Supply, Rev Page ADRF6750 LOWER SIDEBAND CARRIER FEEDTHROUGH SUPPRESSED SIDEBAND THIRD HARMONIC LOWER AND UPPER SECOND HARMONICS 1170 1190 1210 1230 ...
Page 14
... ADRF6750 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 100 1k 10k 100k OFFSET FREQUENCY (Hz) Figure 29. Phase Noise Performance Distribution at Worst-Case Conditions –40 –45 –50 –55 –60 –65 –70 LO FREQUENCY (MHz) Figure 30. Integer Boundary Spur Performance vs. LO Frequency, Supply, and Temperature ...
Page 15
... Figure 40. Attenuator Relative Step Accuracy over all Attenuation Steps vs. LO Frequency for External VCO Mode, Nominal Conditions Rev Page ADRF6750 NOMINAL WORST CASE –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 ATTENUATOR RELATIVE STEP ACCURACY (dB) ...
Page 16
... ADRF6750 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 LO FREQUENCY (MHz) Figure 41. Attenuator Absolute Step Accuracy over all Attenuation Steps vs. LO Frequency, Nominal Conditions ATTENUATOR ABSOLUTE STEP ACCURACY (dB) Figure 42. Attenuator Absolute Step Accuracy Distribution at Nominal and Worst-Case Conditions 1.5 1.0 0.5 0 –0.5 – ...
Page 17
... Rev Page NOMINAL SETTLING TIME TO 0.2dB NOMINAL SETTLING TIME TO 0.5dB WORST-CASE SETTLING TIME TO 0.2dB WORST-CASE SETTLING TIME TO 0.5dB ATTENUATOR SETTLING TIME (µs) ( dB) 0 TURN-ON = 180ns TURN-OFF = 270ns TXDIS 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TXDIS SETTLING TIME (µs) and Temperature ADRF6750 4.0 4.5 5.0 ...
Page 18
... ADRF6750 THEORY OF OPERATION OVERVIEW The ADRF6750 device can be divided into the following basic building blocks: • PLL synthesizer and VCO • Quadrature modulator • Attenuator • Voltage regulator • C/SPI interface Each of these building blocks is described in detail in the sections that follow. ...
Page 19
... PLL acquisition cycle starts, and the LDET signal goes low. When lock has been achieved, this signal returns high. Voltage-Controlled Oscillator (VCO) The VCO core in the ADRF6750 consists of two separate VCOs, each with 16 overlapping bands. Figure 56 shows an acquisition plot demonstrating both the VCO overlap at roughly 1260 MHz and the multiple overlapping bands within each VCO ...
Page 20
... LO Frequency VCO QUADRATURE MODULATOR Overview A basic block diagram of the ADRF6750 quadrature modulator circuit is shown in Figure 60. The VCO generates a signal at the 2× LO frequency, which is then divided down to give a signal at the LO frequency. This signal is then split into in-phase and quadrature components to provide the LO signals that drive the mixers. ...
Page 21
... X7R or X5R capacitors are recommended. See the Evaluation Board section for more information. EXTERNAL VCO OPERATION The ADRF6750 can be operated with an external VCO. This can be useful if the user wants to improve the phase noise performance or extend the frequency range. Note that the external VCO needs to operate at a frequency of 2× ...
Page 22
... Logic 1 on the LSB of the first byte indicates that the master reads information from the peripheral. The ADRF6750 acts as a standard slave device on the bus. The data on the SDA pin (Pin 29) is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADRF6750 has 34 subad- dresses to enable the user-accessible internal registers ...
Page 23
... Figure 68 shows an example of a write operation to the ADRF6750. Data is clocked into the registers on the rising edge of CLK using a 24-bit write command. The first eight bits represent the write command 0xD4, the next eight bits are the register address, and the final eight bits are the data to be written to the specific register ...
Page 24
... ADRF6750 CS CLK SDI START COMMAND [0xD4] CS CLK SDI START COMMAND [0xD4] CS CLK SDI SDO START COMMAND [0xD5 WRITE CS • • • (CONTINUED) CLK • • • (CONTINUED) SDI D7 D6 • • • (CONTINUED) Figure 68 ...
Page 25
... PROGRAM MODES The ADRF6750 has 34 8-bit registers to allow program control of a number of functions. Either an SPI can be used to program the register set. For details about the interfaces and timing, see Figure 63 to Figure 69. The registers are documented in Table 6 to Table 24. ...
Page 26
... ADRF6750 VCO Autocalibration The VCO uses an autocalibration technique to select the correct VCO and band, as explained in the Voltage-Controlled Oscillator (VCO) section. Register CR24, Bit 0, controls whether the auto- calibration is enabled. For normal operation, autocalibration needs to be enabled. However, if using cumulative frequency steps of ...
Page 27
... Read/write Reserved Read/write Lock detector control Read/write Autocalibration Read/write Reserved Read/write Reserved Read/write LO monitor output and External VCO control Read/write Internal VCO power-down Read/write Modulator Read/write Attenuator Read only Reserved Read only Reserved Read only Revision code Rev Page ADRF6750 ...
Page 28
... ADRF6750 REGISTER BIT DESCRIPTIONS Table 7. Register CR0 (Address 0x00), Fractional Word 4 Bit Description 1 7 Fractional Word F7 6 Fractional Word F6 5 Fractional Word F5 4 Fractional Word F4 3 Fractional Word F3 2 Fractional Word F2 1 Fractional Word F1 0 Fractional Word F0 (LSB) 1 Double-buffered. Loaded on the write to Register CR0. ...
Page 29
... Table 18. Register CR23 (Address 0x17), Lock Detector Control Bit Description 7 Reserved 6 Reserved 5 Reserved 4 Lock detector enable 0 = lock detector disabled (default lock detector enabled 3 Lock detector up/down count 0 = 3072 up/down pulses 1 = 2048 up/down pulses 2 Lock detector precision 0 = low, coarse (16 ns high, fine (6 ns) 1 Reserved 0 Reserved Rev Page ADRF6750 ...
Page 30
... ADRF6750 Table 19. Register CR24 (Address 0x18), Autocalibration Bit Description 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Disable autocalibration 0 = enable autocalibration (default disable autocalibration Table 20. Register CR27 (Address 0x1B), LO Monitor Output and External VCO Control Bit Description 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 External VCO control ...
Page 31
... INT and FRAC registers, and starts a new PLL acquisition. If the cumulative frequency step is 100 kHz or less, the user can turn off autocalibration. This process involves an additional write of 0x19 to Register CR24, resulting in a smoother frequency step and shorter acquisition time. Rev Page ADRF6750 ...
Page 32
... PC cable diagram that must be used with the provided software. There is also an option to use the I receptacle connector. This is a standard I resistors are required on the signal lines. The CS pin can be used to set the slave address of the ADRF6750. CS high sets the slave address to 0x60, and CS low sets the slave address to 0x40 ...
Page 33
... PLL. A high level indicates a locked condition, and a low level indicates a loss of lock condition. TXDIS This input disables the RF output. It can be driven from an exter- nal stimulus or simply connected high or low by Jumper J18. RF Output (RFOUT) RFOUT is the RF output of the ADRF6750. RFOUT MOD should be grounded in the user application. Rev Page ADRF6750 ...
Page 34
... ADRF6750 Figure 71. Applications Circuit Schematic Rev Page 08201-072 ...
Page 35
... PCB ARTWORK Component Placement Figure 72. Evaluation Board, Top Side Component Placement Figure 73. Evaluation Board, Bottom Side Component Placement Rev Page ADRF6750 ...
Page 36
... ADRF6750 PCB Layer Information Figure 74. Evaluation Board, Top Side—Layer 1 Figure 75. Evaluation Board, Bottom Side—Layer 4 Rev Page ...
Page 37
... Figure 76. Evaluation Board, Ground—Layer 2 Figure 77. Evaluation Board Power—Layer 3 Rev Page ADRF6750 ...
Page 38
... R17, R18 3 R35, R44, R45 4 R48 to R51 3 R59 to R61 Description ADRF6750 LFCSP, 56-lead 8 mm × VCO, 10 MHz Connector, 9-pin, D-sub plug, SDEX9PNTD 2 Connector SEMCONN receptacle Capacitor, 10 μ tantalum, TAJ-C Capacitor ceramic, C0G, 0402 Capacitor, 100 nF X7R, ceramic, 0603 Capacitor, 220 μ ...
Page 39
... Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel Evaluation Board Rev Page 0.30 0.23 0.60 MAX 0.18 PIN 1 INDICATOR 56 1 4.95 EXPOSED 4.80 SQ PAD 4.65 (BOTTOM VIEW 0.30 MIN 6.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ADRF6750 Package Option CP-56-3 CP-56-3 ...
Page 40
... ADRF6750 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08201-0-1/10(0) Rev Page ...