SCANSTA111 National Semiconductor Corporation, SCANSTA111 Datasheet
SCANSTA111
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SCANSTA111 Summary of contents
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... Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is im- proved test throughput and the ability to remove a board from the system and retain test access to the remaining modules ...
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... Local Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANSTA111 Test Access Port that drives them. The term local was adopted from the system test architecture that the ’STA111 will most commonly be used in; namely, a system test backplane with a ’STA111 on each card driving local scan rings per card. (Each card can contain multiple ’ ...
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... TAP controller. Each local port contains all four boundary scan signals needed to interface with the local TAPs plus the optional Test Reset signal (TRST). FIGURE 1. SCANSTA111 Block Diagram 3 ). This control block receives input from n 10124503 www ...
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No. Pin Name Pins I/O VCC 3 N/A Power GND 3 N/A Ground TMS 1 I BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the B ’STA111. Also controls sequencing of the TAPs which are on the ...
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... The port-selection process is supported by a Level-2 proto- col. HIERARCHICAL SUPPORT - Multiple SCANSTA111’s can be used to assemble a hierarchical boundary-scan tree. In such a configuration, the system tester can configure the local ports of a set of ’STA111s connect a specific set of local scan-chains to the active scan chain ...
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... State Machines (Continued) www.national.com FIGURE 2. SCANSTA111 State Machines 6 10124505 ...
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... Figure 4), one per ’STA111 FIGURE 3. State Machine for SCANSTA111 Selection Controller FIGURE 4. Local SCANSTA111 Port Configuration State Machine The ’STA111’s scan port-configuration state-machine is used to control the insertion of local scan ports into the overall scan chain, or the isolation of local ports from the chain. From the perspective of a system’ ...
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... Level-2 protocol. In addition, the ’STA111 provides a number of Level-2 instructions for func- tions other than local scan port confguration. These instruc- tions provide access to and control of various registers within the ’STA111. This set of instructions includes: FIGURE 5. Relationship Between SCANSTA111 State Machines www.national.com BYPASS EXTEST SAMPLE/PRELOAD ...
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... Once a ’STA111 has been selected, Level-2 protocol is used to issue commands and to access the chip’s various regis- ters. Register Set The SCANSTA111 includes a number of registers which are used for ’STA111 selection and configuration, scan data manipulation, and scan-support operations. These registers can be grouped as shown in Table 3. ...
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... Multi-Cast Group 3 3F Note 4: Hex addresses 80’ to FF’ are only available when using the eighth address bit in the HDL version of the SCANSTA111. The Silicon part has seven address lines and will treat the most-significant address bit as a don’t care. ...
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... FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register Level 2 Protocol Once the SCANSTA111 has been successfully addressed and selected, its internal registers may be accessed via Level-2 Protocol. Level-2 Protocol is compliant to IEEE Std. 1149.1 TAP protocol with one exception: if the ’STA111 is selected via the Broadcast or Multi-Cast address, TDO always TRI-STATED ...
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Level 2 Protocol (Continued) Pause-IR and the active scan chain consists of: TDI through the instruction register (or the IDCODE register) and out through TDO . B → Instruction Register → TDO TDI B The UNPARK instruction (described later) is ...
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Level 2 Protocol (Continued) Instructions Hex Op-Code BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT (Note 5) MODESEL MODESEL 1 MODESEL 2 MODESEL 3 MCGRSEL SOFTRESET LFSRSEL LFSRON LFSROFF CNTRSEL CNTRON CNTROFF DEFAULT_BYPASS (Note 6) TRANSPARENT0 TRANSPARENT1 TRANSPARENT2 TRANSPARENT3 ...
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Level 2 Protocol (Continued) TABLE 5. Level 2 Protocol and Op-Codes (Continued) Instructions Hex Op-Code DGPIO 4 DGPIO 5 DGPIO 6 DGPIO 7 SGPIO 0 SGPIO 1 SGPIO 2 SGPIO 3 SGPIO 4 SGPIO 5 SGPIO 6 SGPIO 7 Other ...
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... CNTROFF: This instruction disables the TCK counter, and TCK control is returned to Mode Register n DEFAULT_BYPASS: This instruction selects the Bypass register to be the default for SCANSTA111 commands that do not explicitly require a data register. The default after RESET is the Device ID register during the Shift-DR state. Data n ...
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... INSTRUCTION REGISTER: The instruction shift register is an 8-bit register that is in series with the scan chain when- ever the TAP Controller of the SCANSTA111 is in the Shift-IR state. Upon exiting the Capture-IR state, the value XXXXXX01 is captured into the instruction register, where XXXXXX represents the value on the S ’ ...
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Register Descriptions TABLE 7. Mode Register Control of LSPN (Continued) Mode Register(s) Scan Chain Configuration (if unparked) → Register → LSP MR0: X000X001 TDI B → Register → LSP MR0: X000X010 TDI B → Register → LSP MR0: X000X011 TDI ...
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Register Descriptions count (zero cleared (logic 0) when the counter is loaded following a CNTRSEL instruction. The power-on value for bit BIT 7 Description TCK Counter Status LSP Used in Silicon Y Default Value 0 ...
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... B instructions will not work in this mode. BIST SUPPORT The sequence of instructions to run BIST testing on a parked SCANSTA111 port is as follows: 1. Pre-load the Boundary register of the device under test if needed. 2. Issue the CNTRSEL instruction and initialize (load) the TCK counter to 00000000 Hex. Note that the TCK counter is initialized to 00000000 Hex upon Test-Logic- Reset, so this step may not be necessary ...
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Special Features (Continued) FIGURE 11. Local Scan Port Synchronization on Second Pass FIGURE 12. Synchronization of the Three Local Scan Ports This moves the local chain TAP Controllers to the synchro- nization state (Run-Test/Idle), where they stay until synchro- nization ...
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Special Features (Continued) • Number/Type of GPIO bits: The STA111 has both dedi- cated and shared GPIO (General Purpose I/O). Each dedicated group of GPIO bits supports from dedi- cated inputs and dedicated outputs. ...
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Special Features (Continued) registers (one register per LSP). The GPIO outouts are updated during the UPDATE-DR state and the GPIO input values are written to the corresponding GPIO register during the CAPTURE-DR state. LSP SHARED: In the shared mode of ...
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Special Features (Continued) FIGURE 13. Address Interrogation State Machine 23 10124504 www.national.com ...
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Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( −0. Input Voltage ( Output Diode Current ( −0. Output Voltage (V ...
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DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter V Maximum Low Output Voltage OL (TRIST , TRIST , LSP_ACTIVE B (0-2) I Maximum Input Leakage Current IN (TCK , ...
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AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified. Symbol Parameter t , Propagation Delay PHL15 t TMS to TMS PLH15 B (0- Propagation Delay PHL16 t TDI to TDO PLH16 B (0-2) ...
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AC Loading and Waveforms FIGURE 14. AC Test Circuit (C FIGURE 15. Waveforms for an Unparked STA111 in the Shift-DR (IR) TAP Controller State includes probe and jig capacitance 6.0V 50pF AC Waveforms 27 10124520 ...
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AC Loading and Waveforms www.national.com (Continued) FIGURE 16. Reset Waveforms FIGURE 17. Output Enable Waveforms 28 10124538 10124539 ...
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AC Loading and Waveforms Waveform for Inverting and Non-inverting Functions Propagation Delay, Pulse Width and t (Input Characteristics 1MHz, t Capacitance & I/O Characteristics Refer to National’s website for IBIS models at http://www.national.com/scan (Continued) 10124521 Tristate Output High ...
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... Physical Dimensions unless otherwise noted www.national.com inches (millimeters) 48-Pin TSSOP NS Package Number MTD48 Ordering Code SCANSTA111MT 49-Pin BGA NS Package Number SLC49a Ordering Code SCANSTA111SM 30 ...
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information ...