PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 27

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.1
When pin TM0=0, PI7C9X110 will be in transparent bridge mode and the configuration registers for transparent
bridge should be used.
When pin TM0=1, PI7C9X110 will be in non-transparent bridge mode and the configuration registers for non-
transparent bridge should be used.
PI7C9X110 supports capability pointer with PCI-X (ID=07h), PCI power management (ID=01h), PCI bridge sub-
system vendor ID (ID=0Dh), PCI Express (ID=10h), vital product data (ID=03h), and message signaled interrupt
(ID=05h). Slot identification (ID=04h) is off by default and can be turned on through configuration programming.
Table 7-1 Configuration Register Map (00h – FFh)
Pericom Semiconductor
CONFIGURATION REGISTER MAP
Primary Bus
Configuration Access
for both Transparent
and Non-Transparent
mode, or Secondary
Bus Configuration
Access for Transparent
Mode
01h - 00h
03h – 02h
05h – 04h
07h – 06h
0Bh – 08h
0Ch
0Dh
0Eh
0Fh
13h – 10h
17h – 14h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Fh – 1Eh
21h – 20h
23h – 22h
25h – 24h
Secondary Bus
Configuration Access
for Non-Transparent
Mode Only
01h – 00h
03h – 02h
45h – 44h
47h – 46h
0Bh – 08h
4Ch
4Dh
4Eh
4Fh
53h – 50h
57h – 54h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Fh – 5Eh
61h – 60h
63h – 62h
65h – 64h
Page 27 of 145
Transparent Mode
(type1)
Vendor ID
Device ID
Command Register
Primary Status
Register
Class Code and
Revision ID
Cacheline Size
Register
Primary Latency Timer
Header Type Register
Reserved
Reserved
Reserved
Primary Bus Number
Register
Secondary Bus
Number Register
Subordinate Bus
Number Register
Secondary Latency
Timer
I/O Base Register
I/O Limit Register
Secondary Status
Register
Memory Base Register
Memory Limit
Register
Prefetchable Memory
Base Register
Non-Transparent
Mode (Type0)
Vendor ID
Device ID
Primary Command
Register
Primary Status
Register
Class Code and
Revision ID
Primary Cacheline Size
Register
Primary Latency Timer
Header Type Register
Reserved
Primary CSR and
Memory 0 BAR
Primary CSR I/O BAR
Downstream I/O or
Memory 1 BAR
Downstream I/O or
Memory 1 BAR
Downstream I/O or
Memory 1 BAR
Downstream I/O or
Memory 1 BAR
Downstream Memory
2 BAR
Downstream Memory
2 BAR
Downstream Memory
2 BAR
Downstream Memory
3 BAR
Downstream Memory
3 BAR
Downstream Memory
3 Upper 32-bit BAR
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
EEPROM
(I2C)
Access
Yes1
Yes1
No
No
Yes1
-
No
No
-
No
No
No
No
No
No
No
No
No
No
No
No
PI7C9X110
SM Bus
Access
Yes5
Yes5
Yes
Yes
Yes5
-
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes