PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 29

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

Pericom Semiconductor
Primary Bus
Configuration Access
for both Transparent
and Non-Transparent
mode, or Secondary
Bus Configuration
Access for Transparent
Mode
73h – 70h
77h – 74h
7Bh – 78h
7Bh – 78h
7Bh – 78h
7Ch
7Dh
7Eh
7Fh
83h – 80h
87h – 84h
8Bh – 88h
8Fh – 8Ch
93h – 90h
97h – 94h
9Bh – 98h
9Fh – 9Ch
A3h – A0h
A7h – A4h
ABh – A8h
Afh – ACh
B3h – B0h
B7h – B4h
BBh – B8h
BFh – BCh
C3h – C0h
C7h – C4h
CBh – C8h
CFh – CCh
D3h – D0h
D6h – D4h
D7h
DBh – D8h
DFh – DCh
Secondary Bus
Configuration Access
for Non-Transparent
Mode Only
73h – 70h
77h – 74h
7Bh – 78h
7Bh – 78h
7Bh – 78h
3Ch
3Dh
3Eh
3Fh
83h – 80h
87h – 84h
8Bh – 88h
8Fh – 8Ch
93h – 90h
97h – 94h
9Bh – 98h
9Fh – 9Ch
A3h – A0h
A7h – A4h
ABh – A8h
Afh – ACh
B3h – B0h
B7h – B4h
BBh – B8h
BFh – BCh
C3h – C0h
C7h – C4h
CBh – C8h
CFh – CCh
D3h – D0h
D6h – D4h
D7h
DBh – D8h
DFh – DCh
Page 29 of 145
PCI-X Capability
Device Capability
Transparent Mode
(type1)
EEPROM (I2C)
Control and Status
Register
Reserved
GPIO Data and
Control (20 bits)
Reserved (12 bits)
Reserved (12 bits)
Reserved
Reserved
Reserved
Reserved
PCI-X Bridge Status
Upstream Split
Transaction
Downstream Split
Transaction
Power Management
Capability
Power Management
Control and Status
Reserved
Reserved
Slot ID Capability
PCI Clock and
CLKRUN Control
SSID and SSVID
Capability
Subsystem ID and
Subsystem Vendor ID
PCI Express Capability
Device Control and
Status
Link Capability
Link Control and
Status
Slot Capability
Slot Control and Status
XPIP Configuration
Register 0
XPIP Configuration
Register 1
XPIP Configuration
Register 2
Reserved
VPD Capability
Register
VPD Data Register
Non-Transparent
Mode (Type0)
EEPROM (I2C)
Control and status
Register
Reserved
GPIO Data and
Control (20 bits)
Bridge Control and
Status (10 bits)
Reserved (2 bits)
Secondary Interrupt
Line
Secondary Interrupt
Pin
Secondary Min_Gnt
Secondary Max_Lat
PCI-X Capability
PCI-X Bridge Status
Upstream Split
Transaction
Downstream Split
Transaction
Power Management
Capability
Power Management
Control and Status
Downstream Memory
0 Translated Base
Downstream Memory
0 Setup
Slot ID Capability
PCI Clock and
CLKRUN Control
Downstream I/O or
Memory 1 Translated
Base
Downstream I/O or
Memory 1 Setup
PCI Express Capability
Device Capability
Device Control and
Status
Link Capability
Link Control and
Status
Slot Capability
Slot Control and Status
XPIP Configuration
Register 0
XPIP Configuration
Register 1
XPIP Configuration
Register 2
Reserved
VPD Capability
Register
VPD Data Register
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
EEPROM
(I2C)
Access
No
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Yes
No
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
3
3
3
4
PI7C9X110
SM Bus
Access
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
3
3
3