MSC8122 Freescale Semiconductor, MSC8122 Datasheet
MSC8122
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MSC8122 Summary of contents
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... SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC8122 MSC8122 FC PBGA–431 20 mm × memory banks for external memories, and 2 memory banks for IPBus peripherals and internal memories. • ...
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... Package Information .44 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 List of Figures Figure 1. MSC8122 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. StarCore SC140 DSP Extended Core Block Diagram . . 3 Figure 3. MSC8122 Package, Top View . . . . . . . . . . . . . . . . . . . . 5 Figure 4. MSC8122 Package, Bottom View . . . . . . . . . . . . . . . . . . 6 Figure 5. Overshoot/Undershoot Voltage for V Figure 6. Start-Up Sequence Figure 7. Start-Up Sequence: V ...
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... Notes: 1. The arrows show the data transfer direction. 2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines Figure 2. StarCore SC140 DSP Extended Core Block Diagram MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor SC140 ...
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... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC8122 package ball grid array layouts and pinout allocation tables. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. ...
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... HD7 HD15 HD9 DDH HD14 HD12 HD10 HD63 DD AB GND HD13 HD11 HD8 HD62 www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Top View GND GND GND GND GND GND ...
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... HD34 HD37 GND DDH HD35 HD38 HD42 HD36 HD39 HD41 HD44 DD www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev Bottom View GND GND GND GND GND GND DD DD ...
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... C5 C6 GPIO28/UTXD/DREQ2 C10 C11 C12 C13 www.DataSheet4U.com C14 C15 C16 GPIO30/TIMER2/TMCLK/SDA C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Table 1. MSC8122 Signal Listing by Ball Designator Des. V C18 DD GND C19 GND C20 NMI_OUT C21 GND C22 V D2 ...
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... F15 ETHRX_CLK/ETHSYNC_IN F16 ETHTX_CLK/ETHREF_CLK/ETHCLOCK F17 GPIO20/TDM1RDAT F18 GPIO18/TDM1RSYN/DREQ2 F19 GPIO16/TDM1TCLK/DONE1/DRACK1 F20 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD F21 GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC F22 GPIO19/TDM1RCLK/DACK2 www.DataSheet4U.com G5 MSC8122 Quad Digital Signal Processor Data Sheet, Rev Des. GND GND G8 GND G9 V G10 DD GND G11 GND G12 G13 G14 ...
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... J21 GPIO25/TDM0RCLK/IRQ15 J22 PWE3/PSDDQM3/PBS3 K6 PWE1/PSDDQM1/PBS1 K7 POE/PSDRAS/PGPL2 K8 IRQ2/BADDR30 K9 K10 K11 K12 K13 www.DataSheet4U.com K14 MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Des. V K15 DDH A31 K16 HA18 K17 HA26 K18 V K19 DD HA13 K20 GND K21 K22 BADDR27 ...
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... N17 N18 N19 PSDWE/PGPL1 N20 GPIO26/TDM0RDAT N21 N22 HWBS3/HDBS3/HWBE3/HDBE3 P7 HWBS2/HDBS2/HWBE2/HDBE2 P8 HWBS1/HDBS1/HWBE1/HDBE1 P9 P10 www.DataSheet4U.com P11 MSC8122 Quad Digital Signal Processor Data Sheet, Rev Des. V P12 DDH HBRST P13 V P14 DDH V P15 DDH GND P16 V P17 DDH A24 P18 A21 ...
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... T21 T22 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 www.DataSheet4U.com U20 MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Des. U21 U22 TSZ0 V2 TSZ2 V3 TBST D16 V6 TT1 V7 D21 V8 D23 V9 V10 ...
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... Y15 Y16 Y17 Y18 HD37/D37/reserved Y19 HD34/D34/reserved Y20 Y21 Y22 AA2 AA3 AA4 AA5 AA6 AA7 HD59/D59/ETHMDIO www.DataSheet4U.com AA8 MSC8122 Quad Digital Signal Processor Data Sheet, Rev Des. V AA9 DDH AA10 V AA11 DDH AA12 GND AA13 GND AA14 A7 AA15 A6 AA16 ...
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... Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC8122. Rating Core and PLL supply voltage ...
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... Reduced (300 and 400 MHz) I/O supply voltage Input voltage Operating temperature range: • Standard • Extended 2.3 Thermal Characteristics Table 4 describes thermal characteristics of the MSC8122 for the FC-PBGA packages. Characteristic 1, 2 Junction-to-ambient Junction-to-ambient, four-layer board 4 Junction-to-board (bottom) 5 Junction-to-case ...
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... DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8122. The measurements in Table 5 assume the following system conditions: • °C A • — 300/400 MHz 1.1 V nominal = 1.07–1.13 V — 400 MHz 1.2 V nominal = 1.14–1.26 V — 500 MHz 1.2 V nominal = 1.16–1.24 V • = 3.3 V ± ...
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... See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design recommendations. The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which raised together. Figure 7 shows a sequence in which www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev 17 DDH ...
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... V 2.2 V 1.2 V o.5 V Figure 6. Start-Up Sequence: V 3.3 V 1.2 V o.5 V PORESET/TRST asserted V applied DD Figure 7. Start-Up Sequence: V www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor V = Nominal Value DDH V = Nominal Value DD 1 PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted V /V Applied DD DDH and V ...
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... Reference clock (REFCLK) frequency www.DataSheet4U.com Output clock (CLKOUT) frequency SC140 core clock frequency Note: The rise and fall time of external clocks should maximum MSC8122 Quad Digital Signal Processor Data Sheet, Rev should always be equal to or less than the ...
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... Host reset command through JTAG All MSC8122 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources. ...
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... Through the direct slave interface (DSI) • Through the system bus. When the reset configuration is written through the system bus, the MSC8122 acts as a configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is written, a default configuration word is applied. ...
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... PORESET Internal HRESET Output (I/O) SRESET Output (I/O) www.DataSheet4U.com Figure 9. Timing Diagram for a Reset Configuration Write MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Characteristics RSTCONF , CNFGS, DSISYNC, DSI64, RSTCONF RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2] pins are sampled ...
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... System Bus Access Timing 2.5.5.1 Core Data Transfers Generally, all MSC8122 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4 ...
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... Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings. 2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge. 3. Guaranteed by design. www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Table 14. AC Timing for SIU Inputs Characteristic 3 3 ...
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... The maximum bus frequency depends on the mode: • In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on. ...
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... AACK/ARTRY/TA/TEA/DBG/BG/BR Data bus inputs—ECC and parity modes Address bus/TS /TT[0–4]/TC[0–2]/ Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor REFCLK 11 PSDVAL/ABB/DBB inputs 12 Data bus inputs—normal mode ...
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... CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode. For designs that use the CLKOUT values specified for synchronization. Figure 12 shows the relationship between the CLKIN www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev to- skew timing. CLKIN Table 16. CLKOUT Skew Characteristic ...
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... DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge signal is synchronized with The DREQ according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction. DACK/DONE/DRACK www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Table 17. DMA Signals Characteristic . To achieve fast response, a synchronized peripheral should assert REFCLK ...
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... Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn. 2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design. 3. All values listed in this table are tested or guaranteed by design. www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev Table 18. DSI Asynchronous Mode Timing Characteristics 2 Min Max 1 ...
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... HTA 4 HTA Notes Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor 100 112 103 107 104 106 108 Used for single-strobe mode access. Used for dual-strobe mode access. ...
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... Figure 16 shows DSI asynchronous broadcast write signals timing. HCS HA[11–29] HCID[0–4] HDST 1 HRW 2 HRDS 1 HDBSn 2 HWBSn HD[0–63] www.DataSheet4U.com Notes: Figure 16. Asynchronous Broadcast Write Timing Diagram MSC8122 Quad Digital Signal Processor Data Sheet, Rev HCS HDST 1 HRW 100 2 112 1 2 106 3 HTA 108 4 HTA ...
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... HCID[0–4] input signals All other input signals HD[0–63] output signals www.DataSheet4U.com HTA output signal Figure 17. DSI Synchronous Mode Signals Timing Diagram MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Table 19. DSI Inputs in Synchronous Mode Expression HTC (0.5 ± 0.1) × HTC (0.5 ± ...
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... Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz. 2. Values are based capacitive load. 3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8122 Reference Manual for details. 4. Values are based capacitive load. TDMxRCLK ...
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... URXD and UTXD inputs rise/fall time 402 UTXD output rise/fall time UTXD, URXD inputs UTXD output www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Table 22. UART Timing Characteristics 401 400 Figure 20. UART Input Timing 402 Figure 21. UART Output Timing ...
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... Table 24. Ethernet Controller Management Interface Timing No. 801 ETHMDIO to ETHMDC rising edge set-up time 802 ETHMDC rising edge to ETHMDIO hold time ETHMDC www.DataSheet4U.com ETHMDIO MSC8122 Quad Digital Signal Processor Data Sheet, Rev Table 23. Timer Timing Characteristics 500 501 502 503 Figure 22. Timer Timing ...
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... ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. ETHREF_CLK ETHCRS_DV ETHRXD[0–1] ETHRX_ER www.DataSheet4U.com ETHTX_EN ETHTXD[0–1] MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Table 25. MII Mode Signal Timing Characteristics 803 Valid Valid Figure 24. MII Mode Signal Timing Table 26 ...
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... REFCLK edge to high impedance on GPIO out 604 GPIO in valid to REFCLK edge (GPIO in set-up time) 605 REFCLK edge to GPIO in not valid (GPIO in hold time) www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev Table 27. SMII Mode Signal Timing Characteristics 808 Valid Valid Figure 26 ...
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... TCK cycle time 702 TCK clock pulse width measured at V • High • Low 703 TCK rise and fall times MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor High Impedance 604 Valid Figure 27. GPIO Timing Table 29. EE Pin Timing Type Asynchronous ...
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... All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. TCK (Input) TCK (Input) Data Inputs Data Outputs Data Outputs www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev Table 30. JTAG Timing (continued) Characteristics 703 Figure 29. Test Clock Input Timing Diagram ...
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... TDO (Output) TCK (Input) TRST (Input) 3 Hardware Design Considerations The following sections discuss areas to consider when the MSC8122 device is designed into a system. 3.1 Start-up Sequencing Recommendations Use the following guidelines for start-up and power-down sequences: • Assert and PORESET required minimum power levels. This can be implemented via weak pull-down resistors. ...
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... GND All output pins on the MSC8122 have fast rise and fall times. PCB trace interconnection length should be minimized to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk ...
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... For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8122 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13. ...
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... CLKIN — Connect the oscillator output through a buffer to — Connect the CLKIN between the clock buffer to the MSC8122 and the SDRAM is equal (that is, has a skew less than 100 ps). — Valid clock modes in this scheme are 15, 19, 21, 23, 28, 29, 30, and 31. • In synchronization mode (for 1 ...
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... I/O The power dissipation values for the MSC8122 are listed in Table 2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...
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... MSC8122 Reference Manual (MSC8122RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8122 device. • SC140 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set ...
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... Added additional guidelines to prevent reverse current to Section 3.1. www.DataSheet4U.com • Added connectivity guidelines for DSI in sliding windows mode to Section 3.3. 15 May 2008 • Changed V MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Table 31. Document Revision History 2 C timing changed to GPIO timing. + 10% changed Figure 2-1 ...
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... Revision History www.DataSheet4U.com MSC8122 Quad Digital Signal Processor Data Sheet, Rev Freescale Semiconductor ...
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... MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor Revision History 47 ...
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... Fax: +1-303-675-2150 LDCForFreescaleSemiconductor www.DataSheet4U.com @hibbertgroup.com Document Number: MSC8122 Rev. 15 5/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...