MB1503 Fujitsu Media Devices, MB1503 Datasheet - Page 5

• Manufacturer Part Number: MB1503
• Description: LOW-POWER PLL FREQUENCY SYNTHESIZER
• Manufacturer: Fujitsu Media Devices

FUNCTIONAL DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
f
Serial data input
Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is input to the Data pin.
One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:
(a)
VCO
= [(M x N) + A] x f
f
N
A
f
R
M
Programmable reference divider ratio
The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The serial 16-bit data format is
shown below:
VCO
OSC
Control data
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of binary 11-bit programmable counter (16 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383)
: Preset divide ratio of modules prescaler (128)
H
L
C
OSC
Destination of serial data
15-bit latch
18-bit latch
S
1
R (A < N)
S
2
Divide ratio setting bit for programmable reference counter
Control bit
LSB
S
3
S
4
S
5
Direction of data shift
S
6
Divide ratio setting bit for prescaler
S
7
S
8
A
127)
S
9
10
S
11
S
MSB
12
S
13
S
14 SW
S
MB1503
5