MB1503 Fujitsu Media Devices, MB1503 Datasheet - Page 7

• Manufacturer Part Number: MB1503
• Description: LOW-POWER PLL FREQUENCY SYNTHESIZER
• Manufacturer: Fujitsu Media Devices

Notes: 1. Divide ratios less than 16 are prohibited for the 11–bit programmable counter
Serial data input timing
Divide
ratio
7-bit swallow counter divide ratio
127
t
t
1
4
A
0
1
( 1 s) : Data setup time
( 1 s) : LE setup time to the rising edge of last clock
Note:
1 : Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.
2. S1 to S7: These bits select the divide ratio of the swallow counter (0 to 127)
3. S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047)
4. C: Control bit: (Set low)
5. Input MSB data first
S
7
0
0
1
One bit of data is shifted into the shift register on the rising edge of the clock.
S
6
0
0
1
Clock
Data
S
5
0
0
1
LE
(Divide ratio = 0 to 127)
S
4
0
0
1
(SW) ( 1)
S18 =
MSB
S
3
0
0
1
t
1
t
S
2
0
0
1
2
( 1 s) : Data hold time
(S14)
S17
S
1
0
1
1
t
2
(S8)
S10
Divide
2047
ratio
11-bit programmable counter divide ratio
16
17
N
S9
(S7)
18
S
0
0
1
17
S
0
0
1
t
t
t
3
5
3
( 1 s) : Clock pulse width
( 1 s) : LE pulse width
16
S
0
0
1
S1 =
(S1)
LSB
15
S
0
0
1
(C: Control bit)
14
S
C: Control bit
0
0
1
t
5
13
S
0
0
1
(Divide ratio = 16 to 2,047)
12
t
S
4
1
1
1
11
S
0
0
1
10
S
0
0
1
MB1503
S
9
0
0
1
S
8
0
1
1
7