MAX1258 Maxim Integrated Products, MAX1258 Datasheet - Page 22

• Manufacturer Part Number: MAX1258
• Description: Multichannel ADCs/DACs
• Manufacturer: Maxim Integrated Products

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12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurements section for details on converting the dig-
ital code to a temperature.
In addition to the 12-bit ADC, the MAX1220–MAX1223/
MAX1257/MAX1258 also include eight voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential non-
linearity error. Each DAC has a 2µs settling time and
ultra-low glitch energy (4nV
unipolar binary with 1 LSB = V
Figure 1 shows the functional diagram of the MAX1257/
MAX1258. The shift register converts a serial 16-bit
word to parallel data for each input register operating
with a clock rate up to 25MHz. The SPI-compatible digi-
tal interface to the shift register consists of CS, SCLK,
DIN, and DOUT. Serial data at DIN is loaded on the
falling edge of SCLK. Pull CS low to begin a write
sequence. Begin a write to the DAC by writing
0001XXXX as a command byte. The last 4 bits of the
DAC select register are don’t-care bits. See Table 10.
Write another 2 bytes to the DAC interface register fol-
lowing the command byte to select the appropriate DAC
and the data to be written to it. See Tables 20 and 21.
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
The MAX1220–MAX1223/MAX1257/MAX1258 DAC out-
put-voltage range is based on the internal reference or
an external reference. Write to the setup register (see
22
______________________________________________________________________________________
•
s). The 12-bit DAC code is
REF
DAC Digital Interface
/ 4096.
12-Bit DAC
Table 5) to program the reference. If using an external
voltage reference, bypass REF1 with a 0.1µF capacitor
to AGND. The MAX1221/MAX1223/MAX1257 internal
reference is 2.5V. The MAX1220/MAX1222/MAX1258
internal reference is 4.096V. When using an external
reference on any of these devices, the voltage range is
0.7V to AV
See Table 2 for various analog outputs from the DAC.
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AV
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AV
at FFFh. While RES_SEL is high, the 100kΩ pullup
resistor pulls the DAC outputs to V
buffers are powered down.
See Table 21 for a description of the DAC power-up
and power-down modes.
Table 2. DAC Output Code Table
MSB
1111
1000
1000
0111
0000
0000
DAC CONTENTS
DD
1111
0000
0000
0111
0000
0000
.
1111
0001
0000
0111
0001
0000
LSB
DAC Power-On Wake-Up Modes
DD
to wake up all DAC outputs
+
V
REF
DAC Transfer Function
ANALOG OUTPUT
DAC Power-Up Modes
+
+
+
+
V
V
V
V
REF1



REF
REF
REF
2048
4096
REF
and the output













 =

0
4095
4096
2047
4096
2049
4096
4096
1



+












V
2
REF
DD



or