MAX1258 Maxim Integrated Products, MAX1258 Datasheet - Page 36

• Manufacturer Part Number: MAX1258
• Description: Multichannel ADCs/DACs
• Manufacturer: Maxim Integrated Products

www.DataSheet4U.com
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
conversion. However, coupled noise may result in
degraded ADC SNR.
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog-input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low.
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition ( CNVST is not required).
36
DOUT
SCLK
EOC
DIN
CS
______________________________________________________________________________________
t
DOV
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
MSB1
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1220–MAX1223/MAX1257/
MAX1258 then power up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. If a temperature measurement is
requested, the temperature result precedes all other
FIFO results. EOC stays low until CS is pulled low again.
Wait until all conversions are complete before reading
the FIFO. SPI communications to the DAC and GPIO
registers are permitted during conversion. However,
coupled noise may result in degraded ADC SNR.
Conversions Using the Serial Interface
Internally Timed Acquisitions and
ADC Conversions in Clock Mode 10
LSB1
MSB2