MAX1258 Maxim Integrated Products, MAX1258 Datasheet - Page 29

• Manufacturer Part Number: MAX1258
• Description: Multichannel ADCs/DACs
• Manufacturer: Maxim Integrated Products

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Table 10. DAC Select Register
Table 11. Reset Register
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11 and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 9) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
byte controls the DAC serial interface. See Table 20
and the DAC Serial Interface section.
FBGON
RESET
NAME
SLOW
NAME
BIT
—
—
—
—
—
BIT
—
—
—
—
X
X
X
X
7 (MSB) Set to zero to select ADC reset register.
0 (LSB)
7 (MSB) Set to zero to select DAC select register.
BIT
12-Bit, Multichannel ADCs/DACs with FIFO,
6
5
4
3
2
1
BIT
6
5
4
3
2
1
0
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to one to select ADC reset register.
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
Set to one to turn on slow mode.
Set to one to force internal bias block and
bandgap reference to be always powered
up.
______________________________________________________________________________________
Set to zero to select DAC select register.
Set to zero to select DAC select register.
Set to one to select DAC select register.
Don’t care.
Don’t care.
Don’t care.
Don’t care.
Temperature Sensing, and GPIO Ports
FUNCTION
FUNCTION
DAC Select Register
Table 12. GPIO Command Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or to reset all registers to their default
states. Set the RESET bit to one to reset the FIFO. Set
the RESET bit to zero to return the MAX1220–MAX1223/
MAX1257/MAX1258 to their default power-up state. All
registers power up in state 00000000, except for the
setup register that powers up in clock mode 10
(CKSEL1 = 1). Set the SLOW bit to one to add a 15ns
delay in the DOUT signal path to provide a longer hold
time. Writing a one to the SLOW bit also clears the con-
tents of the FIFO. Set the FBGON bit to one to force the
bias block and bandgap reference to power up regard-
less of the state of the DAC and activity of the ADC
block. Setting the FBGON bit high also removes the
programmed wake-up delay between conversions in
clock modes 01 and 11. Setting the FBGON bit high
also clears the FIFO.
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1220/MAX1221. The 16 SCLK cycles
GPIOSEL1
BIT NAME
GPIOSEL1
GPIOSEL2
—
—
—
—
—
—
1
1
0
GPIOSEL2
7 (MSB)
0 (LSB)
BIT
6
5
4
3
2
1
1
0
1
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
GPIO write bit.
GPIO configuration; written data is
entered in the GPIO configuration
register.
GPIO write; written data is entered
in the GPIO write register.
GPIO read; the next 8/16 SCLK
cycles transfer the state of all GPIO
drivers into DOUT.
FUNCTION
FUNCTION
GPIO Command
Reset Register
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