WM8581 Wolfson Microelectronics Ltd., WM8581 Datasheet - Page 43

• Manufacturer Part Number: WM8581
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
CLOCK SELECTION
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To accompany the flexible digital routing options, the WM8581 offers a clock configuration scheme
for each interface. By default, the user can choose the interface clock from MCLK, ADCMCLK,
PLLACLK or PLLBCLK, with some restrictions which are autoconfigured. For example, if the S/PDIF
receiver is routed to the DAC, appropriate interface clocks are autoconfigured. These are described
in the following sections.
For some interfaces, the rate can be controlled either by external LRCLK (slave mode), internal
LRCLK (master mode) or by control register. The available options are described below.
It is possible to override the autoconfiguration (setting CLKSEL_MAN = bit 6 of Register 8 to a 1),
allowing the user to manually select any available clock for any interface using the appropriate
CLKSEL register bits.
DAC INTERFACE
The DAC_CLKSEL register selects the DAC clock source from MCLK, PLLACLK or PLLBCLK. If the
digital routing has been set such that the DAC1 is sourcing the S/PDIF Receiver, then PLLACLK is
automatically selected, and DACs 2/3/4 are powered down by default.
With RX2DAC_MODE set, DAC1 sources the S/PDIF receiver and DACs 2,3 and 4 source the PAIF
(and hence are not powered down). The PAIFRX_LRCLK determines the sampling rate, so the
S/PDIF sampling rate must be synchronised with PAIF_LRCLK. Also, use of the S/PDIF receiver
means that PLLACLK and PLLBCLK are not available, and the MCLK applied to the DACs must be
at a standard audio rate.
The rate at which the DACs operate is determined by the DAC Rate module, divided down from the
MCLK signal. It calculates the rate based on the digital routing setup, and selects between
128/192/256/384/512/768/1152fs. When sourcing from the PAIF Receiver, PAIFRX_LRCLK (internal
or external) is used in the rate calculation. When sourcing from the SAIF Receiver, SAIF_LRCLK
(internal or external) is used in the rate calculation. When DAC1 is sourcing directly from the S/PDIF
receiver, the sub-frame clock, SFRM_CLK, is used in the rate calculation. However this can be
changed by setting the RX2DAC_MODE register bit, allowing the PAIF_LRCLK to determine the
sampling rate.
Figure 26 DAC Clock Selection
REGISTER
ADDRESS
R8
BIT
1:0
DAC_CLKSEL
LABEL
DEFAULT
00
DAC clock source
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
DESCRIPTION
PD Rev 4.0 April 2007
WM8581
43