WM8581SEFT Wolfson Microelectronics Ltd., WM8581SEFT Datasheet - Page 40

• Manufacturer Part Number: WM8581SEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8581
CLOCK SELECTION
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To accompany the flexible digital routing options, the WM8581 offers a clock configuration scheme
for each interface. The user can choose the interface clock from MCLK, ADCMCLK, PLLACLK or
PLLBCLK. For some interfaces, the rate can be controlled either by external LRCLK (slave mode),
internal LRCLK (master mode) or by control register. The available options are described below.
DAC INTERFACE
The DAC_CLKSEL register selects the DAC clock source from MCLK, PLLACLK or PLLBCLK. If the
digital routing has been set such that the DAC1 is sourcing the S/PDIF Receiver, then PLLACLK is
automatically selected, and DACs 2/3/4 are powered down. The rate that the DACs operate at is
determined by the DAC Rate module. It calculates the rate based on the digital routing setup. When
sourcing from the PAIF Receiver, PAIFRX_LRCLK (internal or external) is used in the rate
calculation. . When sourcing from the SAIF Receiver, SAIF_LRCLK (internal or external) is used in
the rate calculation. The SFRM_CLK is used in the rate calculation when the DAC1 sources from the
S/PDIF Receiver, however this can be changed by setting the RX2DAC_MODE register bit. With
RX2DAC_MODE set, the PAIFRX_LRCLK determines the rate, and DACs 2/3/4 source the PAIF
Receiver (and are no longer automatically powered down).
Table 32 DAC Clock Control
Figure 25 DAC Clock Selection
REGISTER
ADDRESS
R15
R8
BIT
1:0
8
DAC_CLKSEL
RX2DAC_MODE
LABEL
DEFAULT
00
0
DAC clock source
(only valid when DAC_SRC = 00)
DAC Rate and Power down control
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
0 = SFRM_CLK determines rate,
DACs 2/3/4 powered down
1 = PAIFRX_LRCLK determines
rate, DACs 2/3/4 source PAIFRX
DESCRIPTION
PP Rev 1.0 March 2006
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