MAX525 Maxim, MAX525 Datasheet - Page 10

• Manufacturer Part Number: MAX525
• Description: Low-Power / Quad / 12-Bit Voltage-Output DAC with Serial Interface
• Manufacturer: Maxim

Figure 5 shows the serial-interface timing requirements.
The chip-select pin (CS) must be low to enable the
DAC’s serial interface. When CS is high, the interface
control circuitry is disabled. CS must go low at least
t
erly clock in the first bit. When CS is low, data is
clocked into the internal shift register via the serial-data
input pin (DIN) on SCLK’s rising edge. The maximum
guaranteed clock frequency is 10MHz. Data is latched
into the appropriate MAX525 input/DAC registers on
CS’s rising edge.
The programming command Load-All-DACs-From-Shift-
Register allows all input and DAC registers to be simul-
taneously loaded with the same digital code from the
input shift register. The no operation (NOP) command
leaves the register contents unaffected and is useful
when the MAX525 is configured in a daisy chain (see
the Daisy Chaining Devices section). The command to
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
Table 1. Serial-Interface Programming Commands
“X” = Don’t care
10
CSS
C1
A1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
______________________________________________________________________________________
before the rising serial clock (SCLK) edge to prop-
A0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
16-BIT SERIAL WORD
C1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
1
C0
C0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D11.................D0
MSB
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
LSB
Load input register A; DAC registers unchanged.
Load input register B; DAC registers unchanged.
Load input register C; DAC registers unchanged.
Load input register D; DAC registers unchanged.
Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.
Update all DAC registers from their respective input registers (start-up).
Load all DAC registers from shift register (start-up).
Shutdown (provided PDL = 1)
UPO goes low (default)
UPO goes high
No operation (NOP) to DAC registers
Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers
updated.
Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers
updated (default).
change the clock edge on which serial data is shifted
out of DOUT also loads data from all input registers to
their respective DAC registers.
The serial-data output, DOUT, is the internal shift regis-
ter’s output. The MAX525 can be programmed so that
data is clocked out of DOUT on SCLK’s rising edge
(Mode 1) or falling edge (Mode 0). In Mode 0, output
data at DOUT lags input data at DIN by 16.5 clock
cycles, maintaining compatibility with Microwire™,
SPI™/QSPI™, and other serial interfaces. In Mode 1,
output data lags input data by 16 clock cycles. On
power-up, DOUT defaults to Mode 0 timing.
The user-programmable logic output, UPO, allows an
external device to be controlled via the MAX525 serial
interface (Table 1).
User-Programmable Logic Output (UPO)
FUNCTION
Serial-Data Output (DOUT)