ICE1232 IC Ensemble, ICE1232 Datasheet - Page 27

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ICE1232

Manufacturer Part Number
ICE1232
Description
ac 97 2.1 VSR Audio Codec With 3D
Manufacturer
IC Ensemble
Datasheet

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Preliminary
Power Management ( continued... )
Test Mode Operation
ATE Test Mode: (PCB in-circuit Testing of the ICE1232)
ATE Test mode is entered when the SDATA_OUT signal is sampled at the rising edge of the RESET# signal.
In this mode, the SDATA_IN and BIT_CLK pins are placed in a high impedance (Hi-Z) state. This mode of
operation doesn’t occur under normal operating conditions.
Vendor Test Mode:
Vendor Test mode is entered when the SYNC signal is sampled during the rising edge of the RESET# signal.
This mode of operation doesn’t occur under normal operating conditions.
Rev. 1.5, 1/10/00
Figure 13. AC’97 Power Down Procedure with Analog Section Still Active
Note: To power up the codec, a warm reset is required; PR4 is reset to zero upon either reset.
Normal
PR0=1
ADC=1
PR0=0
&
ADC’s OFF
PR0
PR1=1
DAC=1
PR1=0
&
DAC’s OFF
PR1
PR4=1
Warm Reset
Digital I/F
OFF
PR4
Shut Off
ICE1232
27

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