XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 61
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
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3.1 Introduction
3.2 Programming Model
M68HC12B Family — Rev. 8.0
MOTOROLA
Data Sheet — M68HC12B Family
The CPU12 is a high-speed, 16-bit processor unit. It has full 16-bit data paths and
wider internal registers (up to 20 bits) for high-speed extended math instructions.
The instruction set is a proper superset of the M68HC11instruction set. The CPU12
allows instructions with odd byte counts, including many single-byte instructions.
This provides efficient use of ROM space. An instruction queue buffers program
information so the CPU always has immediate access to at least three bytes of
machine code at the start of every instruction. The CPU12 also offers an extensive
set of indexed addressing capabilities.
CPU12 registers are an integral part of the CPU and are not addressed as if they
were memory locations. See
15
15
15
15
15
7
A
Central Processor Unit (CPU)
0
Figure 3-1. Programming Model
PC
SP
D
X
Y
Section 3. Central Processor Unit (CPU)
S
7
X
Figure
H
I
B
3-1.
N
Z
V
0
0
0
0
0
0
C
8-BIT ACCUMULATORS A AND B
16-BIT DOUBLE ACCUMULATOR D (A : B)
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
CONDITION CODE REGISTER
CARRY
OVERFLOW
ZERO
NEGATIVE
IRQ INTERRUPT MASK (DISABLE)
HALF-CARRY FOR BCD ARITHMETIC
XIRQ INTERRUPT MASK (DISABLE)
STOP DISABLE (IGNORE STOP OPCODES)
Data Sheet
61
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