MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet
MT58L1MY18P
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MT58L1MY18P Summary of contents
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... Micron’s Web site—http://www.micron.com/numberguide. 2. Contact factory for availability of Industrial Temperature devices. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ™ ...
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... BWa# controls DQa pins/ balls and DQPa; BWb# controls DQb pins/balls and 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM DQPb; BWc# controls DQc pins/balls and DQPc; BWd# controls DQd pins/balls and DQPd ...
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... Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball descriptions, and tim- ing diagrams for detailed information. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM Figure 3: Functional Block Diagram ...
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... No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2. Pins 39 and 38 are reserved for address expansion, 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... NF/DQPc DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd. NF/DQPd 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... No Function: These pins are internally connected to the die and have the capacitance of an input pin. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM DESCRIPTION Micron Technology, Inc ...
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... No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2. Balls 2R and 2P are reserved for address expansionely, 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... DQb balls; byte “c” is associated with DQc balls; byte “d” is associated with DQd DQd balls. Input data must meet setup and hold times around the rising edge of CLK. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM DESCRIPTION Micron Technology, Inc ...
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... No Function: These balls are internally connected to the die and have the capacitance of an input pin. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM DESCRIPTION Micron Technology, Inc ...
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... WRITE All Bytes WRITE All Bytes NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM SECOND ADDRESS THIRD ADDRESS (INTERNAL) X ...
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... BWE# LOW or GW# LOW for the subsequent L–H edge of CLK. Refer to WRITE timing diagram for clarification. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... Output Low Voltage Supply Voltage Isolated Output Buffer Supply 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, ...
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... Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM £ +70º CONDITIONS SYMBOL ...
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... Note 6; notes appear following parameter tables on page 17 DESCRIPTION Junction to Ambient (Airflow of 1m/s, two-layer board) Junction to Case (Top) Junction to Board (Bottom) 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM CONDITIONS T = 25º MHz ...
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... All inputs £ ³ 0.2; Cycle time ³ DD Snooze Mode 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM Operating Conditions and Maximum Limits £ +70º SYM TYP ...
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... Write signals t WH (BWa#-BWd#, BWE#, GW#) Data- Chip enables (CE#, CE2#, t CEH CE2) 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM £ +70º MIN MAX MIN MAX MIN 5 ...
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... Test conditions as specified with the output load- ing shown in Figures 11 and 12 for 3.3V I/O and 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM (GND). Figures 13 and 14 for 2.5V I/O unless otherwise noted. KC/2 for I £ ...
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... driven until after the following clock rising edge. (This note applies to whole diagram.) 4. Outputs are disabled within one clock cycle after deselect. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa#, and BWb# LOW for x18 device; or GW# HIGH and BWE#, BWa#–BWd# LOW for x32 and x36 devices. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... Back-to-back READs may be controlled by either ADSP# or ADSC#. 6. This undefined READ will follow any WRITE cycle which is transitioned to a Read, Deselect, or Snooze. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... SUPPLY I ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM becomes a logic HIGH setup time pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pend- ing operations are completed ...
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... Figure 12: +3.3V Q 351 NOTE: For Figures 11 and 13, 30pF = distributive test jig capacitance. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2. /2.2) + 1.5V Input pulse levels .................... /2.2) - 1.5V ...
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... NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. ...
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... Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM The Boundary Scan Order tables show the order in which the bits are connected ...
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... SRAM clock operates more than an order of magnitude faster. Because there is a large difference in 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM the clock frequencies possible that during the Capture-DR state, an input or output will undergo a transition ...
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... CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figures 18 and 19. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and Operation Conditions tables. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2.5V TAP AC Test Conditions to 3 ...
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... SAMPLE/PRELOAD 100 RESERVED 101 RESERVED 110 111 BYPASS 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM BIT CONFIGURATION DESCRIPTION 0000 Reserved for version number. 00111 Defines depth of 1Mb. 00110 Defines depth of 512K ...
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... ADV# 34 ADSP# 35 ADSC# 36 OE# (G#) 37 BWE# 38 GW# 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM BALL ID BIT 11P 10R ...
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... ADV# 34 ADSP# 35 ADSC# 36 OE# (G#) 37 BWE# 38 GW# 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM BALL ID BIT 11P 10R ...
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... DQPb ADV# 34 ADSP# 35 ADSC# 36 OE# (G#) 37 BWE# 38 GW# 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM BALL ID BIT 11P 10R ...
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... NOTE: 1. All dimensions in inches (millimeters) 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM Figure 20: 100-Pin Plastic TQFP (JEDEC LQFP) 0 ...
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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and SyncBurst are trademarks and/or service marks of Micron Technology, Inc. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ...
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... Corrected grammatical errors • New ADVANCE data sheet for 0.16µm process; Rev. A, Pub. 6/02 ..........................................................................6/02 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ...