MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 2

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

ADSP#, ADV#), byte write enables (BWx#), and global
write (GW#).
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data out (Q) is
enabled by OE#. WRITE cycles can be from one to two
bytes wide (x18) or from one to four bytes wide (x32/
x36), as controlled by the write control inputs.
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst
advance input (ADV#).
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins/balls and DQPa; BWb# con-
trols DQb pins/balls and DQPb. During WRITE cycles
on the x32 and x36 devices, BWa# controls DQa pins/
balls and DQPa; BWb# controls DQb pins/balls and
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
Asynchronous inputs include the output enable
Burst operation can be initiated with either address
Address and write control are registered on-chip to
2
PIPELINED, SCD SYNCBURST SRAM
DQPb; BWc# controls DQc pins/balls and DQPc; BWd#
controls DQd pins/balls and DQPd. GW# LOW causes
all bytes to be written. Parity bits are only available on
the x18 and x36 versions.
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state
of clock.
erPC pipelined systems and systems that benefit from
a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
sramds) for the latest data sheet.
DUAL VOLTAGE I/O
function. The 2.5V V
I/O function.
18Mb: 1 MEG x 18, 512K x 32/36
This device incorporates a single-cycle deselect fea-
The device is ideally suited for Pentium and Pow-
Please refer to Micron’s Web site
The 3.3V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DD
KQHZ nanoseconds after the rising edge
device is tested for 3.3V and 2.5V I/O
DD
device is tested for only 2.5V
(www.micron.com/
©2003 Micron Technology, Inc.