MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 8

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 2:
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
MODE (LBO#)
SYMBOL
OE#(G#)
ADSC#
ADSP#
BWb#
BWd#
BWE#
ADV#
BWa#
BWc#
CE2#
GW#
DQb
DQd
TMS
DQa
DQc
TCK
CE#
CE2
CLK
SA0
SA1
TDI
SA
ZZ
FBGA Ball Descriptions
Output
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,
causing a new extrnal address to be registered. A READ or WRITE is performed using the new
address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is
HIGH.
Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,
causing a new external address to be registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.
ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.
Synchcronous Address Advance: This active LOW input is used to advance the internal burst
counter, controlling busrt access after the external address is loaded. A HIGH on ADV#
effectively causes wait states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an
ADSP# cycle is initiated.
Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a
WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK.
BWs need to be asserted on the same cycle as the address. To enable the BW’s functionality, the
byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa balls; BWb# controls
DQb balls; BWc# controls DQc balls; and BWd# controls DQa balls.
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the
setup and hold times around the rising edge of CLK.
Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the
internal use of ADSP#. CE# is sampled only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only
when a new external address is loaded.
Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded.
Clock: This signal registers the address, data, chip enable, byte write enables, and burst control
inputs on its rising edge. All synchronous inputs must meet setup and hold times around the
clock’s rising edge.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent
of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of
CLK.
Mode: This input selects the burst sequence. A LOW on this ball selects “linear burst.” NC or
HIGH on this ball selects “interleaved burst.” Do not alter input state while device is operating.
LBO# is the JEDEC-standard term for MODE.
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is
the JEDEC-standard term for OE#.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK.
IEEE 1149.1 test inputs: JEDEC-standard 3.3V or 2.5V I/O levels. These balls may be left as No
Connects if the JTAG function is not used in the circuit.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This ball has an internal pull-down and can be left unconnected.
SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa pins; byte “b” is associated
with DQb balls. For the x32 and x36 versions, byte “a” is associated with DQa balls; byte “b” is
associated with DQb balls; byte “c” is associated with DQc balls; byte “d” is associated with DQd
balls. Input data must meet setup and hold times around the rising edge of CLK.
8
PIPELINED, SCD SYNCBURST SRAM
18Mb: 1 MEG x 18, 512K x 32/36
DESCRIPTION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.