MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 11

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 7:
Notes: 1–8
NOTE:
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#) and BWE# are LOW
3. BWa# enables WRITEs to DQa pins/balls and DQPa. BWb# enables WRITEs to DQb pins/balls and DQPb. BWc# enables
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L–H edge of CLK. A WRITE is performed by setting one or more
DESELECT Cycle,
Power-Down
DESELECT Cycle,
Power-Down
DESELECT Cycle,
Power-Down
DESELECT Cycle,
Power-Down
DESELECT Cycle,
Power-Down
SNOOZE MODE,
Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
WRITEs to DQc pins/balls and DQPc. BWd# enables WRITEs to DQd pins/balls and DQPd. DQPa and DQPb are only
available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.
HIGH throughout the input data hold time.
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L–H edge of CLK. Refer to WRITE timing
diagram for clarification.
OPERATION
Truth Table
ADDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
USED
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE#
H
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
11
PIPELINED, SCD SYNCBURST SRAM
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
18Mb: 1 MEG x 18, 512K x 32/36
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
©2003 Micron Technology, Inc.
CLK
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D