MT90401 Zarlink Semiconductor, MT90401 Datasheet

MT90401

Manufacturer Part Number

MT90401

Description

Sonet/sdh System Synchronizer

Manufacturer

Zarlink Semiconductor

Datasheet

1.MT90401.pdf (38 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MT90401AB

Manufacturer:

ZARLINK

Quantity:

500

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MT90401AB1

Manufacturer:

Quantity:

421

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Features

•

Meets requirements of GR-253-CORE for SONET

Stratum 3 and SONET minimum clock

Meets requirements of GR-1244-CORE Stratum 3

Meets requirements of G.813 Option 1 and Option

2 for SDH Equipment Clocks (SEC) with external

jitter attenuator

Provides OC-3/STM-1, DS3, E3, 19.44MHz, DS2,

E1, T1, 8kHz and ST-BUS clock outputs

Accepts reference inputs from two independent

sources

Selectable 1.544MHz, 2.048MHz, 19.44MHz or

8kHz input reference frequencies

Holdover accuracy of 0.02 ppm

Adjustable output clock phase supporting master-

slave arrangements

Hardware or microprocessor control (8 bit

microprocessor interface)

3.3V supply

JTAG boundary scan

Secoor

Prioor

TRST

RSEL

C20i

TMS

TCK

TDO

SEC

TDI

PRI

RST

Reference

MS1 MS2

Monitor

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Reference

1149.1a

Master Clock

Select

IEEE

MUX

Control State Machine

HOLDOVER

Reference

Select

Corrector

Selected

Enable

Refer-

ence

TIE

Figure 1 - Functional Block Diagram

PCCi

Corrector

Circuit

TCLR

TIE

FLOCK

Zarlink Semiconductor Inc.

Select

State

Reference

D0/D7 A0/A6 CS,DS,R/W

Virtual

Applications

•

Description

The MT90401 is a digital phase locked loop (DPLL)

that is designed to synchronize SDH (Synchronous

Digital Hierarchy) and SONET (Synchronous Optical

Network) networking equipment. The MT90401 is used

to ensure that the timing of outgoing signals remains

within the limits specified by Telcordia, ANSI and the

ITU during normal operation and in the presence of

disturbances on the incoming synchronization signals.

LOCK

SONET/SDH System Synchronizer

SONET/SDH Add/Drop multiplexers

SONET/SDH uplinks

Integrated access devices

ATM edge switches

Impairment

Feedback

Monitor

DPLL

Input

MT90401AB

VDD

Select

State

VSS

Ordering Information

-40 C to +85 C

FS1

Frequency

Interface

Output

Select

Circuit

MUX

80 Pin LQFP

FS2

Data Sheet

MT90401

November 2003

C155P/N

C19o

C1.5o

C2o

C4o

C6o

C8o

C16o

C44/C34

F0o

F8o

F16o

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