MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 14

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulses and clock
outputs are locked to one another for all operating states, and are also locked to the selected input reference in
Normal Mode. See Figure 18.
All frame pulses and clock outputs have limited driving capability, and should be buffered when driving capacitive
loads exceeding 30pF.
1.6
This circuit monitors the input signal to the DPLL and automatically enables the Auto-Holdover when the frequency
of the incoming signal is outside the Auto-Holdover capture range. (See Performance Characteristics - Mode
Switching). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When
the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the
input signal. The holdover output signal in the MT90401 is based on the incoming signal 30ms (minimum) to 60ms
prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover
Mode is very accurate (i.e., 0.02ppm). Consequently, the phase delay between the input and output after switching
back to Normal Mode is preserved.
Input Impairment Monitor
Figure 5 - Output Interface Circuit Block Diagram
DPLL
From
Tapped
Tapped
Tapped
Tapped
Tapped
Delay
Delay
Delay
Delay
Delay
Line
Line
Line
Line
Line
Zarlink Semiconductor Inc.
MT90401
8.5/11.2MHz
12MHz
16MHz
19MHz
12MHz
14
DS2 Divider
E1 Divider
T1 Divider
x4 / x8 PLL
C155P/N
C34/C44
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
C6o
C19o
Data Sheet