MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 11

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

MT90401
Data Sheet
TCLR
Resets Delay
Control Signal
Control
Circuit
Delay Value
Virtual
Programmable
Reference to
Delay Circuit
PRI or SEC
DPLL
from
Reference
Select Mux
Compare
Circuit
TIE Corrector
Feedback
Enable
Signal from
from
Frequency
State Machine
Select MUX
Figure 3 - TIE Corrector Circuit
The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,
no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change
at the input of the DPLL, or at the output of the DPLL.
Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual
reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.
This phase error is a function of the difference in phase between the two input reference signals during reference
rearrangements. Each time a reference switch is made, the delay between input signal and output signal will
change. The value of this delay is the accumulation of the error measured during each reference switch.
The programmable delay circuit can be reset to zero by applying a logic low pulse to the TIE Circuit Clear (TCLR)
pin. A minimum reset pulse width is 300ns. This results in a phase realignment between the input reference signal
and the output signal as shown in Figure 16. The speed of the phase alignment correction is limited to 885 ns/s in
SONET mode and 53ns per 1.326 ms in SDH mode, convergence is in the direction of least phase travel.
The state diagram of Figure 12 indicates the state changes for which the TIE Corrector Circuit is activated.
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Zarlink Semiconductor Inc.