MT9122AE Zarlink Semiconductor, MT9122AE Datasheet
MT9122AE
Related parts for MT9122AE
MT9122AE Summary of contents
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... Echo Canceller A Echo Canceller B Figure 1 - Functional Block Diagram PWRDN IC F0od F0i Tone Detection Data Sheet ISSUE 5 September 1996 Ordering Information MT9122AP 28 Pin PLCC MT9122AE 28 Pin PDIP -40 ° °C conforming to ITU-T operates in two major modes: Linear/ Sout µ/A-Law Disable Tone ...
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MT9122 1 ENA1 28 2 ENB1 27 ENA2 ENB2 25 5 Rin 24 PDIP Sin 6 23 VSS MCLK NLP 19 11 REV 18 LAW 12 17 FORMAT 13 ...
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Data Sheet Pin Description (continued) Pin # Name 5 Rin Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may be in either companded or 2’s complement linear format. Two PCM channels are time- ...
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MT9122 Pin Description (continued) Pin # Name 17/18 S4/S3 Selection of Echo Canceller B Functional States (Input): Controllerless Mode: Selects Echo Canceller B functional states according to Table 2. Controller Mode: S4 and S3 pins become SCLK and CS pins ...
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Data Sheet Functional Description The MT9122 architecture contains two individually controlled echo cancellers (Echo Canceller A and B). They can be set in three distinct configurations: Normal, Back-to-Back and Extended Delay (see Figure 3). Under Normal configuration, the two echo ...
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MT9122 Adaptive Filter The adaptive filter is a 1024 tap FIR filter which is divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal configuration, the first section is dedicated to channel A and ...
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Data Sheet where 0 < NLPTHR < 1 (dec) The comfort noise injection can be disabled by setting the INJDis bit Control Register 1. It should be noted that the NLPTHR is valid and the comfort noise ...
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MT9122 Controllerless Mode The NBSD is always active and automatically disables the filter adaptation process when narrow band signals are detected. Controller Mode The NBSD can be disabled by setting the NBDis bit Control Register 2. Offset ...
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Data Sheet for Bypass state, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and Sin to Sout paths have a delay of ...
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MT9122 device determines the mode of operation by monitoring the signal applied to the F0i pin. When a valid ST-BUS frame pulse is applied to the F0i pin, the MT9122 will assume ST-BUS operation. If F0i is tied continuously to ...
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Data Sheet detectors must be limited to the maximum dynamic range specified in G.711 (+3.14 or +3.17 dBm0). Linear PCM data must be formatted as 14-bit, 2’s complement data with three bits of sign extension in the most significant positions ...
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MT9122 Function selected when pins CONFIG1 & 2 ≠ 00 Normal Configuration Set pins CONFIG1 to 1 and CONFIG2 1 to select this configuration. Back-to-Back Set pins CONFIG1 to 1 and CONFIG2 select Configuration this configuration. Extended ...
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Data Sheet C4i F0i F0od ECA PORT1 Rin Sout ECA PORT2 Sin Rout outputs=High impedance inputs = don’t care In ST-BUS Mode 1, both ...
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MT9122 C4i F0i 0 F0od PORT1 Rin Sout PORT2 Sin ...
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Data Sheet BCLK PORT1 ENA1 ENB1 Rin Sout PORT2 ENA2 ENB2 Sin Rout outputs=High impedance inputs = don’t care Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2 ...
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MT9122 COMMAND/ADDRESS DATA 2 R Receive DATA 1 High Impedance Transmit ➁ SCLK CS ➂ ➀ Delays due to internal processor timing which are transparent to the MT9122. ➁ The MT9122: latches receive ...
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Data Sheet Register Summary Echo Canceller A, Control Register 1 CRA1 Reset INJDis BBM Echo Canceller B, Control Register 1 CRB1 Reset INJDis BBM Extended- When high, Echo Cancellers A and B are internally ...
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MT9122 Echo Canceller A, Flat Delay Register Echo Canceller B, Flat Delay Register Echo Canceller A, Decay Step Number Register Echo Canceller B, Decay Step Number Register ...
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Data Sheet Echo Canceller A, Rin Peak Detect Register 2 Echo Canceller B, Rin Peak Detect Register Echo Canceller A, Rin Peak Detect Register 1 Echo Canceller B, Rin ...
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MT9122 Echo Canceller A, Double-Talk Detection Threshold Register 2 ADDRESS = 15h WRITE/READ VERIFY Echo Canceller B, Double-Talk Detection Threshold Register 2 ADDRESS = 35h WRITE/READ VERIFY DTDT DTDT DTDT DTDT Echo Canceller A, Double-Talk ...
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Data Sheet Applications MT8910 2B1Q MT8972 Bi-Phase MT8931 S-INT DSTo T R DSTi echo C4o F0b paths Figure 12 - (Basic Rate ISDN) Wireless Application Diagram MT9160 5V CODEC Dout T Din R F0i Clockin echo path MT9160 5V CODEC ...
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MT9122 MT9160 5V CODEC Dout T Din R F0i Clockin echo path MT9160 5V CODEC Dout T R Din Clockin F0i echo path MT8941 PLL F0 C4 Figure 14 - (Analog Trunk) Wireless Application Diagram MT8910 2B1Q MT8972 Bi-phase MT8931 ...
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Data Sheet Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any digital pin 3 Continuous Current on any digital pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under ...
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MT9122 AC Electrical Characteristics Voltages are with respect to ground (V ) unless otherwise stated. SS Characteristics 1 MCLK Clock High 2 MCLK Clock Low 3 MCLK Frequency Dual Channel Single Channel 4 BCLK/C4i Clock High 5 BCLK/C4i Clock Low ...
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Data Sheet AC Electrical Characteristics Characteristics 1 Input Data Setup 2 Input Data Hold 3 Output Data Delay 4 Serial Clock Period 5 SCLK Pulse Width High 6 SCLK Pulse Width Low 7 CS Setup-Intel 8 CS Setup-Motorola 9 CS ...
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MT9122 Bit 0 (1) Sout/Rout (2) BCLK SSS V (2) ENA1/ENA2 H or (2) V ENB1/ENB2 L Bit (3) Rin/Sin V L Notes: 1. CMOS output 2. TTL input compatible ...
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Data Sheet (1, 2) DATA1 t IDS V H (2) SCLK CSSI Notes: 1. CMOS output 2. TTL input compatible 3. CMOS input (see Table 8 for symbol definitions) V ...
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MT9122 Notes: 28 Data Sheet ...
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