MT9122AE Zarlink Semiconductor, MT9122AE Datasheet - Page 11

• Manufacturer Part Number: MT9122AE
• Description: Description = Dual Voice Echo CANceller ( Itu-t G165 Compliant) With Disable Tone Detection ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
detectors must be limited to the maximum dynamic
range specified in G.711 (+3.14 or +3.17 dBm0).
Linear PCM data must be formatted as 14-bit, 2’s
complement data with three bits of sign extension in
the most significant positions (i.e.: S,S,S,12,11,
...1,0) for a total of 16 bits where “S” is the extended
sign bit. When A-Law is converted to 2’s complement
linear format, it must be scaled up by 6dB (i.e. left
shifted one bit) with a zero inserted into the least
significant bit position. See Figure 8.
Bit Clock (BCLK/C4i)
The BCLK/C4i pin is used to clock the PCM data in
both SSI (BCLK) and ST-BUS (C4i) operations.
In SSI operation, the bit rate is determined by the
BCLK frequency. This input must contain either eight
or sixteen clock cycles within the valid enable strobe
window. BCLK may be any rate between 128 KHz to
4.096 MHz and can be discontinuous outside of the
enable strobe windows defined by ENA1, ENB1,
ENA2 and ENB2 pins. Incoming PCM data (Rin, Sin)
are sampled on the falling edge of BCLK while
outgoing PCM data (Sout, Rout) are clocked out on
the rising edge of BCLK. See Figure 17.
In ST-BUS operation, connect the system C4
(4.096MHz) clock to the C4i pin.
Master Clock (MCLK)
A nominal 20MHz master clock (MCLK) is required
for execution of the MT9122 algorithms. The MCLK
input may be asynchronous with the 8KHz frame. If
only one channel operation is required, (Echo
Canceller A only) the MCLK can be as low as
9.6MHz.
Microport
The serial microport provides access to all MT9122
internal read and write registers and it is enabled
when CONFIG1 and CONFIG2 pins are both set to
logic 0. This microport is compatible with Intel MCS-
51 (mode 0), Motorola SPI (CPOL=0, CPHA=0), and
National Semiconductor Microwire specifications.
The microport consists of a transmit/receive data pin
(DATA1), a receive data pin (DATA2), a chip select
pin (CS) and a synchronous data clock pin (SCLK).
The MT9122 automatically adjusts its internal timing
and pin configuration to conform to Intel or Motorola/
National requirements. The microport dynamically
senses the state of the SCLK pin each time CS pin
becomes active (i.e. high to low transition). If SCLK
pin is high during CS activation, then Intel mode 0
timing is assumed. In this case DATA1 pin is defined
as a bi-directional (transmit/receive) serial port and
DATA2 is internally disconnected. If SCLK is low
during CS activation, then Motorola/National timing
is assumed and DATA1 is defined as the data
transmit pin while DATA2 becomes the data receive
pin. The MT9122 supports Motorola half-duplex
processor mode (CPOL=0 and CPHA=0). This
means that during a write to the MT9122, by the
Motorola processor, output data from the DATA1 pin
must be ignored. This also means that input data on
the DATA2 pin is ignored by the MT9122 during a
valid read by the Motorola processor.
All data transfers through the microport are two bytes
long. This requires the transmission of a Command/
Address byte followed by the data byte to be written
or read from the addressed register. CS must remain
low for the duration of this two-byte transfer. As
shown in Figures 10 and 11, the falling edge of CS
indicates to the MT9122 that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
between the MT9122 and the microcontroller. At the
end of the two-byte transfer, CS is brought high
again to terminate the session. The rising edge of CS
will tri-state the DATA1 pin. The DATA1 pin will
remain tri-stated as long as CS is high.
Intel processors utilize Least Significant Bit (LSB)
first transmission while Motorola/National processors
use Most Significant Bit (MSB) first transmission.
The MT9122 microport automatically accommodates
these two schemes for normal data bytes. However,
to ensure timely decoding of the R/W and address
information, the Command/Address byte is defined
differently for Intel and Motorola/National operations.
Refer to the relative timing diagrams of Figures 10
and 11.
Receive data is sampled on the rising edge of SCLK
while transmit data is clocked out on the falling edge
of SCLK. Detailed microport timing is shown in
Figure 19 and Figure 20.
MT9122
11