MT92210 Zarlink Semiconductor, MT92210 Datasheet
MT92210
Related parts for MT92210
MT92210 Summary of contents
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... Dual M em ory Controler SSRAM SSRAM SSRAM (256k x18*) (512k x18*) (256k x36*) Mem ory Bank ory Bank B Figure 1 - MT92210 Block Diagram MT92210 1023 Channel Voice Over IP Processor Data Sheet Issue 2 Ordering Information MT92210 608 Pin EPBGA -40°C to +85°C ...
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... Voice over DSL/cable Description The MT92210 device is a voice over IP/RTP assembly and disassembly engine that can convert up to 1023 full- duplex PCM voice channels or 4096 HDLC channels to IP packets and back, conforming to IETF RFC791 (IPv4), RFC2460 (IPv6), RFC768 (UDP) and RFC1889 (RTP). On one side, the device communicates with an H.110 TDM bus carrying voice in either PCM format, ADPCM or HDLC-encapsulated mini-packets ...
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... Document Organization This data sheet is divided into the following sections: • CPU Interface (Chapter 2.0) describes the main external interface of the MT92210 chip. • Network Interface (Chapter 3.0) describes the interface to the 3 different types of link interfaces, Ethernet, UTOPIA, and Packet over SONET, that are supported. ...
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... Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 Intel/Motorola Interface 2.3.1 Extended Indirect Access Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1.1 Extended Indirect Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1.2 Extended Indirect Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.2 Extended Direct Access Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.2.1 Extended Direct Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.2.2 Extended direct reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 MT92210 Reset Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.0 Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.0 Link Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 Ethernet Interface 4.3 Packet over SONET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5 Packet Reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 ...
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... AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.5.1 Intel/Motorola CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.5.2 UTOPIA / POS-PHY / Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.5.3 H.110 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.5.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Appendix 179 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Appendix 181 HDLC Format, Including Zero-Insertion and Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Appendix 183 Standards & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 vi Table of Contents Zarlink Semiconductor Inc. ...
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... Data Sheet Appendix .185 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table of Contents Zarlink Semiconductor Inc. MT92210 vii ...
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... Table of Contents Zarlink Semiconductor Inc. ...
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... Data Sheet Figure 1 - MT92210 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i Figure 2 - Internal Interrupt Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3 - Network Interface Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 4 - Packet Block Memory and Format Figure 5 - Packet Block Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6 - Packet Handler Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7 - Handle Queue and Handle Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8 - Basic Handle Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 9 - Raw Cell Format (used cell Figure 10 - Raw Cell Format (free cell) ...
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... Figure 88 - Multiplexed CPU Interface - Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 89 - UTOPIA / POS-PHY / Ethernet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 90 - H.110 Input Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 91 - H.110 Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 92 - External Memory Timing (both SSRAM and SDRAM 177 Figure 93 - Supported RTP HDLC Packet Format (after zero extraction 181 x List of Figures Zarlink Semiconductor Inc. ...
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... Table 41 - Fields and Description 117 Table 43 - Fields and Description 120 Table 44 - Fields and Description 121 Table 45 - Fields and Description 123 Table 46 - Fields and Description 125 Table 47 - Fields and Description 129 Table 48 - Clock Divisor X and 135 Table 49 - Clock Divisor 136 List of Tables Zarlink Semiconductor Inc. MT92210 xi ...
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... Table 50 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table Write Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Table Read Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Table 53 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 54 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 55 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 xii List of Tables Zarlink Semiconductor Inc. ...
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... Data Sheet 1.0 Features The MT92210 device supports the following features: 1.1 General Features • 1023 full-duplex PCM or ADPCM voice channels over IP/UDP/RTP connections • 4096 HDLC channels carrying application data (UDP payload) converted to IP/UDP connections • Simultaneous support of PCM, ADPCM and HDLC connections • ...
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... Non-voice packets can be injected and received via the CPU Interface • Non-voice packets can be injected and received via the secondary UTOPIA port • The MT92210 can be daisy-chained to other UTOPIA devices to increase capacity • Off-the-shelf AAL5 SAR can be used to terminate data connections on a PCI bus • ...
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... Transmission of voice to secondary port allows H.110/PCM bridging when coupled with AAL5 SAR • Pin-out allows designs that support Ethernet, ATM and Packet over SONET with only software configuration deciding on the link layer used Zarlink Semiconductor Inc. MT92210 15 ...
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... The CPU interface can be configured to operate in either Intel or Motorola mode, The MT92210 supports both 8-bit or 16-bit data bus and multiplexed or non-multiplexed address/data pins. Internally, a subset of registers -- CPU Interface Registers (000h to 00Ah), can be accessed with very low latency. ...
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... Interrupt1 Enable (0218h) interrupt1_active_level 18 b10 Status Bits internal interrupt AND OR Interrupt Enable Bits Global Service Register (0210h) AND OR Interrupt interrupt2_active_level Frequency Controler interrupt1 Figure 2 - Internal Interrupt Network Zarlink Semiconductor Inc. b0 AND Interrupt2 Enable (021Ch) OR interrupt2 ...
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... Intel/Motorola Interface The MT92210 CPU interface supports both Intel and Motorola modes, in both 8-bit or 16-bit data bus and multiplexed or non-multiplexed address/data pins. The MT92210 supports 128 Megabytes of addressable space, therefore extended addressing is necessary. The CPU interface directly addresses four control words, delegated for indirection accessing ...
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... Table 4 - Read/Write Data Register (004h) Type Reset RW 0000h Extended address bits 32:20. extended_a[32:0] points to bytes. Used both for extended indirect and extended direct accesses. RO 000 Table 5 - Address High Register (008h) Zarlink Semiconductor Inc. Description Description Description ...
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... CPU address bus. Similarly, the data is fetched/placed directly on the CPU data bus. The access address is written to registers 008h and 00Ah. This will perform only the page addressing. Upon assertion of the address within the page, the MT92210 will read/write the data with respect to that address. The Reset 0000h Extended address bits 19:4 ...
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... MT92210 Reset Procedure The reset procedure for the MT92210 requires several steps, mostly due to the fact that there are several levels of hardware and software resets in the chip. All register accesses in the reset procedure maybe performed in either Direct or Indirect mode. The procedure to configure the chip is as follows: 1 ...
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... Data Sheet 3.0 Network Interface The objective of the MT92210 device is to transport voice information encapsulated in IP packets over network connections. Therefore, to allow maximum flexibility, it can support 3 different types of link interfaces: Ethernet, UTOPIA and Packet over SONET. The network module of the chip is responsible for the identification and routing of packets, deciding which packets should be kept and treated as voice, which should be routed to the data packet buffer and which should be discarded ...
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... Payload Payload Payload Payload Payload Payload Payload Payload Payload Payload Payload Payload Multicast Sum Figure 5 - Packet Block Format Zarlink Semiconductor Inc. b12 b11 b10 Payload Payload Payload Payload Payload Payload Payload Payload Payload ...
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... Used in TX. When packet is queued in multiple TX queues this is decremented each time the packet is sent and the TX queue that decrements frees the cell memory. Table 7 - Packet Block Format Table n size. Note that while handles may be copied to a new Zarlink Semiconductor Inc. MT92210 25 ...
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... Blocks in Queue [18:0] Service Block Fill [18:2] Figure 6 - Packet Handler Memory Description Table 8 - Handle Queue Descriptor Zarlink Semiconductor Inc. b12 b11 b10 Handle Queue Base Address & Size [20:11] Handle Write Pointer [14:0] ...
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... RTD Blocks in Packet[10:0] Figure 8 - Basic Handle Format Zarlink Semiconductor Inc. HRP HWP b12 b11 b10 SOP Handle[18:0] EOP Handle[18:0] Total Packet Length[15:0] MT92210 27 ...
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... Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload PN Figure 9 - Raw Cell Format (used cell) Description Table 9 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 AAL5 VC Number [15:0] b3 ...
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... Cell Payload Cell Payload Figure 10 - Raw Cell Format (free cell) Description Points to the next free cell in SSRAM. Table 10 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 Link to Next Free Cell [20:6] n MT92210 size between 64 29 ...
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... Format of 8 Read Pointer Queue b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 Figure 11 - Cell Handler Memory Zarlink Semiconductor Inc. Reserved Reserved b12 b11 b10 Read FIFO Cell Base Address [20:6] Read FIFO Cell Base Address [20:6] ...
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... In addition to its primary network interface, the MT92210 supports a secondary UTOPIA port that can be used to connect a data SAR to the chip daisy chain several MT92210 chips together. This secondary port is always a UTOPIA port, independently of the configuration of the primary port. The chip is capable of treating IP packets from both ports and can convert from one link layer to the other if need be ...
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... MT92210 can interface with the same external SAR in all modes with minimal changes. Cells received on the secondary UTOPIA port, as well as any cells received on the primary port when it is configured to operate in ATM mode, navigate through the UTOPIA module to reach their final destination. To multiplex and de-multiplex traffic, the UTOPIA module uses input and output FIFO to contain cells ...
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... TX Link B Raw Cell Buffer 0; “xxx1xxxxx” Link B Raw Cell Buffer 1; “xx1xxxxxx” CPU Raw Cell Buffer; “x1xxxxxxx” = reserved; “100000000” = AAL5 VC; Table 11 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 AAL5 VC Struct Base [20:5] Description MT92210 ...
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... Packet Reassembly When communicating only IP packets, the MT92210 can use Ethernet, Packet over SONET or ATM as its primary network interface. The primary interface must be a Utopia bus to carry AAL0 cells, other ATM cells that can carry signaling, and packets broken down and carried over AAL5. Any packets transmitted or received over AAL5 on the link will be done so one cell at a time, contrarily to Ethernet and Packet over SONET, which both transfer and receive entire IP packets ...
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... Connection Cell Count [23:0] Connection Packet Byte Count Flow Table Pointer [26:3] Figure 15 - Packet Reassembly Structure Zarlink Semiconductor Inc. Register A20h Ethernet/POS port Packet Reassembly Struct b12 b11 b10 Max Packet Size [15:0] Next Cell Handle [18:0] SOP Handle [18:0] MT92210 ...
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... This counter excludes the Next Cell Handle, since this handle has been seized for a cell that has not yet arrived. Next Cell Handle Pointer to the block that has been pre-allocated for storing the next cell payload when it is received. 36 Description Table 12 - Fields and Description Zarlink Semiconductor Inc. ...
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... VC on which the packet is carried (in the case of ATM). This field can be overridden later on by protocols that allow VCs to carry packets on multiple subnets, such as LANEv2 or MPOA. The Flow Table Pointer points to a single bit in SSRAM C. Description Table 12 - Fields and Description Zarlink Semiconductor Inc. MT92210 37 ...
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... This chapter describes the data flows for all packets received and transmitted. 5.1 RX Data Flow This section resumes the typical propagation of voice data throughout the MT92210 in the receive direction, from the link to the H.110 bus. Packets arriving off the link are written into memories, either a cell input FIFO if the link is configured as a UTOPIA interface packet input FIFO if the link is configured as an Ethernet or Packet over SONET interface ...
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... A = Ethernet/ POS Legend: Structure in Internal Memory Structure in SSRAM A Structure in SSRAM B Structure in SSRAM C Structure in SDRAM C Figure Flow 1 Zarlink Semiconductor Inc. UTOPIA look-up table (1 per port) UTOPIA0 UTOPIA RX B From link B input FIFO (global) UTOPIA look-up UTOPIA RX A input FIFO ...
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... Profile) ID1 type) ID2 Identifi- cation Key (pre- Identification CRC) Binary Tree Key CRC + Search hashing RTP Data Figure Flow 2 Zarlink Semiconductor Inc. MT92210 Profile Next Memory Header (Option + Memory TOS) (global) (global) ID1 ID4 Packet Identification Packet Buffer Handles ...
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... Packet Disassembly Process: Performs dejittering on xxPCM data, copies payload into circular buffer, performs policing on HDLC & CPU channels, reports errors & events in the Event Report Queue. Figure Flow 3 Zarlink Semiconductor Inc. Payload Type/Marker Bit Table (1 per connection) PTM1 RX RTP Connection ...
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... TX Data Flow The following section summarizes the typical propagation of voice data throughout the MT92210 in the transmit direction, from the H.110 bus to the packet link. Data from a TSST is read off the H.110 bus and is associated with either an xxPCM buffer or an HDLC stream by the TX channel association memory ...
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... Structure (1 per Stream) TXTDM1 Stream) TXTDM1 TX Channel TX Channel TX TDM TX TDM Association Association Process Process Memory (1 entry Memory (1 entry per TSST) TXTDM0 per TSST) TXTDM0 TX xxPCM TX xxPCM Buffer Structure Buffer Structure (1 per Bearer) (1 per Bearer) TXTDM1 TXTDM1 Figure Flow 1 Zarlink Semiconductor Inc. ...
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... Assembly Event Queue (global) Service EVENTQ0-7 Indicator Process Service Indicator Table (up to 16, (1 entry per global) SERVTIM0 Figure Flow 2 Zarlink Semiconductor Inc. MT92210 Packet Assembly TX RTP Connection Identification Structure (1 per Counter Source Connection) (1 per SRC/DST ASSEM0-1 IP Address pair) TX Silence TX RTP Header ...
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... TX link A HP Packet Copying Buffer Handles Process (global) NET6 TX link A LP Packet Buffer Handles (global) NET6 TX link B HP Packet Buffer Handles (global) NET6 Network CPU Packet TX link B LP Packet Buffer Handles Buffer Handles (global) NET6 (global) NET6 Figure Flow 3 Zarlink Semiconductor Inc. ...
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... A cell FIFO into contiguous packets which are then written in the TX link A Packet/Cell FIFO. Also takes care of all Ethernet/POS formatting, such as removing the LANEv1 header. TX link B Cell TX Link B FIFO (global) Copy Process Figure Flow 4 Zarlink Semiconductor Inc. MT92210 TX link link A Packet/Cell FIFO (global link B 47 ...
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... MPOA tag, and the LANEv2 ELAN-ID. Table 13 lists all the packet types that MT92210 can identify. Each type has an associated Initial Search Structure, which has a fixed location in SDRAM C. Any received packet must fall into one of the type, and will be handled as per the instructions in Initial Search Structure ...
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... IPv6 with Fragmented UDP Protocol/non-UDP Protocol/Invalid Protocol 7 IPvX (Other than version ELAN-ID Lookup 9 MPOA Look-up 10 MPLS Look-up Table 13 - Packet Types and Initial Search Structures 50 Packet Type Zarlink Semiconductor Inc. Initial Search Structure ID Key Address in SDRAM Format 1000h 3 1080h - 1100h 1 1180h 1 ...
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... Packet Parsing Before getting to the IP level, the MT92210 must parse through all of the link-layer information and headers contained in the packet. The MT92210 can support packets whose link-layer information begins with an LLC header (Classical IP over ATM, LANE v2), a PPP header (Packet over SONET, PPP over ATM), an Ethernet header (Ethernet, LANE v1), an MPOA tag (MPOA over ATM), an MPLS label header or application data ...
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... With this ability, the MT92210 can ensure that any packet containing a certain header will be deleted or always sent to the CPU buffer, for example. The information indicating how to treat the various “next header” values is contained in the Next Header memory. ...
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... N*16 to N*16+15, where N is the profile entry number. In this way, all 256 values for the options are treated. These values are not in any way linked to the profile; they just reside in the same memory. Table 15 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 ...
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... Table 15 - Fields and Description b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 Figure 29 - Flow Table Zarlink Semiconductor Inc. MT92210 b12 b11 b10 I253 b1 b0 I31 ...
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... Table 17 - Profile Default Post-Search Structure 56 Description Table 16 - Fields and Description Profile Default Post-Search Structure Address in SDRAM 1800h 1880h 1900h 1980h 1A00h 1A80h 1B00h 1B80h 1C00h 1C80h 1D00h 1D80h 1E00 1E80 1F00 1F80 Zarlink Semiconductor Inc. ...
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... FFFFh Match Packet Count [31:0] Match Byte Count [31:0] Next Profile (Refer to Table 19 for field descriptions) Zarlink Semiconductor Inc. b13 b12 b11 b10 FFFFh RTD RUN MT92210 ...
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... Header CRC Key [55:32] Header CRC Key [31:0] First Post-Search Confirmation Structure Address [24:7] Figure 31 - Binary Tree Node Description Table 18 - Fields and Description Zarlink Semiconductor Inc. b12 b11 b10 Right Address [19: ...
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... The format of the post-search confirmation structure is indicated in the next figure. Zarlink Semiconductor Inc. MT92210 59 ...
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... Identification Key Dword 9 Flow Table Pointer [23:0] Match Packet Count [31:0] Match Byte Count [31:0] Next Profile LHR New ATM Header HP [31:0] CPI HP [7:0] New ATM Header LP [31:0] CPI LP [7:0] Figure 32 - Post-Search Conformation Structure Zarlink Semiconductor Inc. b13 b12 b11 b10 RTP Connection Structure Base Address [20:5] ...
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... This index points to an entry within the Flow table that corresponds to the Destination IP Flow Table) address of this packet. Note that the old Flow Table Pointer will be used to look-up the IP Address Index, even if the Flow Table Pointer is changed by this structure. Description Table 19 - Fields and Description Zarlink Semiconductor Inc. MT92210 61 ...
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... Then the chip will repeat the above search procedure with using the Destination IP address and the Destination UDP port, and come back to the matching post-search confirmation structure. This time, the required destination is the packet disassembly module. Thus the packet is sent to the disassembly module and the next packet can be treated. 62 Description Table 19 - Fields and Description Zarlink Semiconductor Inc. ...
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... Packet Assembly The MT92210 packet assembly module is responsible for collecting the bytes written in the circular buffers by the TX TDM and assembling them into RTP packets. Bytes will usually be encapsulated into RTP, UDP and IP, and then be shipped off on Ethernet, ATM or Packet over SONET; the packet assembly can also support a multitude of other header combinations ...
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... Service Timer Descriptor 13 Service Timer Descriptor 14 Service Timer Descriptor 15 b11 b10 Indicators per Frame Service Timer Base Address [20:5] Next Indicator to be Read [15:0] Last Indicator Number [15:0] Figure 33 - Service Timer Control Memory Table 20 - Fields and Description Zarlink Semiconductor Inc ...
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... Indicator 0 +4 Indicator 1 +8 Indicator 2 Indicator N-3 Indicator N-2 Indicator N 65536} Start Boundary = 16 bytes b11 b10 b11 b10 Serv Timer # Assembly Structure Base Address [20:6] Table 21 - Service Timer Zarlink Semiconductor Inc. MT92210 ...
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... For example, the sequence number will be incremental across all packets on an IP/RTP connection, not just on voice packets generated by the chip. 66 Description +0 Assembly Event 0 +10 Assembly Event 1 +20 Assembly Event 2 +(N-3)*10h Assembly Event N-3 +(N-2)*10h Assembly Event N-2 +(N-1)*10h Assembly Event N {1024, 2048, 4096} Start/Cross Boundary = {16K, 32K, 64K} bytes Figure 34 - Assembly Event Queue Zarlink Semiconductor Inc. ...
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... Local Bus Time Stamp during which the HDLC packet completed. b12 b11 b10 Assembly Structure Base Address [20:6] CPU Packet Base Address [20:5] TDM Write Pointer [13:0] CPU Packet Length [10:0] Buf Size Time Stamp [31:16] Time Stamp [15:0] Description Table 22 - Fields and Description Zarlink Semiconductor Inc. MT92210 ...
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... Table 23 - Fields and Description b13 b12 b11 b10 Assembly Structure Base Address [20:6] CPU Packet Base Address [20:5] TDM Write Pointer [13:0] Buf Size CPU Packet Length [10:0] Time Stamp [31:16] Time Stamp [15:0] Zarlink Semiconductor Inc Description ...
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... UDP header is always 8 bytes, while the link header can end on any byte boundary. In the structure, padding bytes and will be added to the link header: it must always end on a dword Description Table 24 - Fields and Description Zarlink Semiconductor Inc. MT92210 69 ...
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... HDLC/CPU packets), or the first 12 bytes of RTP header for PCM packets, are copied into external memory. For HDLC/CPU channel carrying RTP, the first 12 bytes will represent the mandatory fields of the RTP 70 14 identification values can be contained in external memory, and each Zarlink Semiconductor Inc. ...
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... Data Sheet header. With this information, RTCP packets can be generated without requiring communication between the host on which the MT92210 is running and the source of the HDLC data stream. 7.3.9 RTD The RTD field (RouTing Destination) indicates where this packet will be destined in the network interface. In most applications it will be set to transmit packets to port A, but the field allows flexibility by allowing the possibility of internal loopback, sending to port B, or other destinations ...
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... Word of Last RTP Packet Record of first 6 words of last transmitted RTP payload. These fields can be used Sent to monitor what is being sent on this connection. Note This structure must begin on a 64-byte boundary. 72 Description Table 25 - Fields and Description Zarlink Semiconductor Inc. ...
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... Fifth Word of Last RTP Packet Sent Sixth Word of Last RTP Packet Sent Bearer 1 - Circular Buffer Base Address [20:9] Bearer 2 - Circular Buffer Base Address [20:9] Bearer N-2 - Circular Buffer Base Address [20:9] Bearer N-1 - Circular Buffer Base Address [20:9] Zarlink Semiconductor Inc Extra Delay Frames [7:0] Number of Channels [7:0] MT92210 73 ...
Page 74
... Bearers For each bearer in this xxPCM channel, a single circular buffer base address must be specified in one of these extension words. All xxPCM channels will have between 1 and 255 bearers, thus between 1 and 255 extension words. 74 Definition Table 26 - Fields and Description Zarlink Semiconductor Inc. ...
Page 75
... TX Link A LP; “xxx1xxxxx” Link B LP; “xxxx1xxxx” Link B HP; “xxxxx1xxx” = reserved; “xxxxxx1xx” = Network CPU Packet Buffer; “xxxxxxx1x” = reserved; “000000001” = Packet Identifier. Table 27 - Fields and Description Zarlink Semiconductor Inc Packet Type Header Length [9:2] Description MT92210 75 ...
Page 76
... Header Words - Padding. Position in bytes of the first byte of the 802.3 Ethertype/Length with respect to Header word 0. Points to the dword of the IPv6 header, relative to Header Word 0, in which the packet identification field will be written. Table 27 - Fields and Description (continued) Zarlink Semiconductor Inc. Description ...
Page 77
... IP and UDP (or null) headers and transmitted as such. The assembly process, in addition to encapsulating the payload in these protocols, may perform some RTP functions. The Sequence Number Insert bit indicates whether the RTP sequence number should be generated by the structure or kept the payload. Zarlink Semiconductor Inc. MT92210 77 ...
Page 78
... Timestamp Insert bit to '0' and the Timestamp Offset well. By setting the Sequence Number Insert bit to '0' and making the timestamp transparent as described above, non-RTP packets can also be sent through HDLC or the CPU port. 78 Zarlink Semiconductor Inc. ...
Page 79
... The silence suppression information can also be fed to the process externally. When this is the case, a special PCM code is used on the TDM bus. In this mode, 2 TSSTs must be used to feed the MT92210 with the transmit data. When the last PCM byte of the packet is read off the H.110 bus is 00h and the associated time slot upper bit also indicates 0, this means that the packet must be suppressed ...
Page 80
... Finally, instead of calculating its own CN energy and generating the packet itself, the MT92210 can use a preprogrammed CN packet. This preprogrammed packet can be of variable length, allowing spectral data to be passed along as well as an energy value. Preprogrammed packets must be written into external SSRAM agent through the CPU interface and may be updated periodically ...
Page 81
... Energy Sum [15:0] Energy Counter [12:0] Underrun Count [15:0] Energy Increase Threshold [7:0] amp_iir_fall_length ceiling_exp_half_life [15:0] floor_exp_half_life [15:0] ceiling_exp_start_v max_floor_level [12:0] min_threshold_while_talking [12:0] min_threshold_while_silent [12:0] flux_min_threshold [12:0] First Energy Period [12:0] Subsequent Energy Period [12:0] Zarlink Semiconductor Inc Maximum dB Value [6:0] Type 0 HPE BL holdover_counter [5:0] LS amp_iir [21:16] Energy Sum [38:32] holdover_time [6:0] flux_ratio [4:0] ratio_while_talking [7:0] MT92210 81 ...
Page 82
... HP 10Hz Context [15:0] floor_exp [4:0] holdover_talk_counter [6:0] floor_latch [12:0] ceiling_latch [12:0] CTS LS amp_iir [15:0] ceiling_exp_half_life_counter [15:0] floor_exp_half_life_counter [15:0] Preprog Packet Length - 1 Preprogrammed Packet Pointer[16:2] Underrun Count amp_iir_fall_length ceiling_exp_half_life [15:0] floor_exp_half_life [15:0] ceiling_exp_start_v max_floor_level [12:0] min_threshold_while_talking [12:0] min_threshold_while_silent [12:0] flux_min_threshold [12:0] Zarlink Semiconductor Inc Type 0 HPE BL holdover_counter [5:0] amp_iir [21:16] Preprog Pnt [20:17] holdover_time [6:0] flux_ratio [4:0] ratio_while_talking [7:0] ...
Page 83
... Figure Silence Suppression Structure: External VAD & White Energy Estimation b13 b12 b11 b10 Correction [7:0] Minimum dB Value [6:0] Latched Energy Energy Sum [31:16] Energy Sum [15:0] Energy Counter [12:0] Underrun Count First Energy Period [12:0] Subsequent Energy Period [12:0] Zarlink Semiconductor Inc Maximum dB Value [6:0] Type 1 Energy Sum [38:32] Energy Increase Threshold MT92210 83 ...
Page 84
... Figure Silence Suppression Structure: External VAD & Spectral Energy Forwarding 84 b13 b12 b11 b10 Preprog Packet Length - 1 Preprogrammed Packet Pointer [16:2] Underrun Count Zarlink Semiconductor Inc Type 1 Preprog Pnt [20:17] ...
Page 85
... Should be initialized to zero by software. Should be initialized to zero by software. Last sent energy level exactly as it was sent in the comfort noise description packet. Accumulator used to estimate the idle line energy level. Must be initialized to zero by software. Table 28 - Fields and Description Zarlink Semiconductor Inc. Description MT92210 85 ...
Page 86
... Length of the preprogrammed comfort noise packet in bytes (minus 1). To send single byte comfort noise packets (the basic non-spectral mode), this field must be set to 00h. This field points to the location in SSRAM A at which the preprogrammed packet is located. Table 28 - Fields and Description (continued) Zarlink Semiconductor Inc. Description ...
Page 87
... CPU the HDLC bus). +0 Event 0 +10 Event 1 +(N-2)*10h Event N-2 +(N-1)*10h Event N-1 Figure Disassembly Event Report Queue Zarlink Semiconductor Inc. MT92210 87 ...
Page 88
... Structure Address from the RX connection structure and the RX Channel structure is read. This structure may be in the xxPCM, HDLC or CPU format. If the Type field in the RX Connection Structure associated to the RX Channel Structure is delete, then no RX Channel structure will be read and the packet will be deleted. Otherwise, the RX Channel structure is read and interpreted according to its type. 88 Zarlink Semiconductor Inc. ...
Page 89
... Received Octet Count [31:16] Received Octet Count [15:0] Type RX RTP Channel 0 Structure Address [20:5] Type RX RTP Channel 15 Structure Address [20:5] Figure RTP Connection Structure Description Table 29 - Fields and Description Zarlink Semiconductor Inc Net Jitter Fraction [3:0] PCM Info PCM Info MT92210 89 ...
Page 90
... Report UUI/LI Combination to CPU through the RX Disassembly Event Report Queue (when set). Type Type of RX RTP Channel Structure. “000” = PCM + ADPCM; “001” = HDLC; “010” CPU; “111” = delete; others = reserved. 90 Description Table 29 - Fields and Description (continued) Zarlink Semiconductor Inc. ...
Page 91
... Table 29 - Fields and Description (continued) b13 b12 b11 b10 Entry 1 Entry 5 Entry 249 Entry 250 Entry 253 Entry 254 Figure 47 - Payload Type/Marker Bit Table Description Table 30 - Fields and Description Zarlink Semiconductor Inc Entry 3 Entry 2 Entry 7 Entry 6 Entry 251 Entry 255 MT92210 91 ...
Page 92
... RVM UCE BL1 RX RTP Connection Base Address [20:5] Payload Type [6:0] UDP Payload Length [7:0] Previous RTP Sequence Number [15:0] This RTP Sequence Number [15:0] Local Bus Time Stamp [31:16] Local Bus Time Stamp [15:0] Description Table 31 - Fields and Description Zarlink Semiconductor Inc ...
Page 93
... RX xxPCM channel structures can generate clock recovery pulses to the clock recovery module to indicate the arrival of packets. The MT92210 allows 2 redundant clock recovery circuits to run simultaneously, so the extension structures contain 2 bits, clock recovery A and clock recovery B, which the structure used to generate pulses. When it generates packet arrival pulses to the clock recovery module, the disassembly process also sends it the timestamp and the sequence number of the current packet (if RTP is being used) ...
Page 94
... Received Octet Count [15:0] Channel 0 - Circular Buffer Base Address [20:8] Channel 1 - Circular Buffer Base Address [20:8] Channel 2 - Circular Buffer Base Address [20:8] Channel 253 - Circular Buffer Base Address [20:8] Channel 254 - Circular Buffer Base Address [20:8] Figure RTP xxPCM Channel Structure Zarlink Semiconductor Inc ...
Page 95
... RPM bit will be cleared automatically by the hardware. When PDV monitoring is reset, the Minimum Delta and Maximum Delta are set to the delta of the first packet received in the new PDV monitoring period. Table 32 - Fields and Description Zarlink Semiconductor Inc. MT92210 95 ...
Page 96
... RX xxPCM Channel structure (to identify the channel to which the report structure belongs), the current Local Bus Timestamp and the current Remote Timestamp. 96 Table 32 - Fields and Description (continued) Zarlink Semiconductor Inc. ...
Page 97
... Offset Delta has been reset in the Common PDV Absorption structure. Samples lost. When set, the Samples Lost[31:0] field is non-zero, meaning that one or many samples have been lost between packets. Table 33 - Fields and Description Zarlink Semiconductor Inc BL4 BL3 XD 0 Description MT92210 97 ...
Page 98
... Packet Delay Variation (PDV) Monitoring The MT92210's PDV monitoring writes packets within a PDV window, minimizing delay while trying to avoid slips this, it writes packets based on their remote timestamp: a packet's position in the circular buffer is decided by its RTP timestamp. This allows compensation for packet loss and misinsertion. ...
Page 99
... K samples of delay are ever inserted on the data. The MT92210 PDV monitoring may be used to control the end-to-end delay experienced on a given channel so, the software initializes the Desired Remote/Local Timestamp Delta field to 0. This gives the expected delta between the timestamp in the RTP packet and the timestamp on the H ...
Page 100
... Remote/Local Time Stamp Delta. Setting this bit gives controlling software full control of the de-jittering functionality. This field contains the local 32-bit bus time stamp that was present when the last received packet was processed by the PDV monitoring block. Table 34 - Fields and Description Zarlink Semiconductor Inc ...
Page 101
... This value is the current number of frames either added or dropped due to overruns and underruns. A positive number represents overruns and a negative number represents underruns. Note that underrun frames and overruns frames cancel-out in this field. Table 34 - Fields and Description (continued) Zarlink Semiconductor Inc. Description MT92210 101 ...
Page 102
... This field should be written to zero at initialization time. Write 0 for normal operation. all remote/local time stamp deltas are calculated with the following equation: delta = remote_packet_timestamp - local_bus_timestamp; Table 34 - Fields and Description (continued) Zarlink Semiconductor Inc. Description ...
Page 103
... Before writing the HDLC RTP packet in its circular buffer, the disassembly performs all of the header, CRC and zero-insertion functions. The MT92210 supports 2 types of HDLC framing: bit-wise and byte-wise framing (see Annex for more details). The appropriate form of framing is applied to the entire packet (including headers and CRC) before the packet is written in its circular buffer ...
Page 104
... Initialized bit. Written to zero by software channel initialization. Written to ‘1’ by hardware as soon at the first packet is received on this channel. Received Packet Count Total number of packets received on this channel so far. Every packet that gets to this structure will be included. 104 Description Table 35 - Fields and Description Zarlink Semiconductor Inc. ...
Page 105
... Channel Structure Address [20:5] RX Connection Structure Address [20:5] Packet Base Pointer [15:0] Packet Length [11:0] Local Bus Time Stamp [31:16] Local Bus Time Stamp [15:0] Description Table 36 - Fields and Description Zarlink Semiconductor Inc MT92210 105 ...
Page 106
... RX CPU Buffer Control Structure 511 b12 b11 b10 Circular Buffer Base [20:8] and Size Circular Buffer Write Pointer [15:0] Circular Buffer Read Pointer [15:0] Figure CPU Buffer Control Table Description Table 37 - Fields and Description Zarlink Semiconductor Inc Add ...
Page 107
... MT92210 107 ...
Page 108
... Discharge Rate [5:0] Maximum Bucket Fill [15:0] Last Packet Local Time Stamp [23:8] I Current Bucket Fill [15:0] Received Packet Count [15:0] Received Octet Count [31:16] Received Octet Count [15:0] Figure RTP CPU Channel Structure Description Table 38 - Fields and Description Zarlink Semiconductor Inc 0x00 ...
Page 109
... Received Octet Count Total number of bytes received on this channel so far. Every packet that gets to this structure will be included. This field increments by the UDP Length - 8 each time packet is received. Table 38 - Fields and Description (continued) Zarlink Semiconductor Inc. Description MT92210 109 ...
Page 110
... Zarlink Semiconductor Inc. ...
Page 111
... The TX TDM section of the chip takes bytes from the H.110 interface and writes them into circular buffers in SSRAM so, the MT92210 uses the TX Channel Association Memory to decide which of the 1023 time slots on the H.110 bus it wants to treat. Each entry in the TX Channel Association Memory associates a time slot with either a PCM buffer or an HDLC stream ...
Page 112
... PCM buffer or an HDLC stream. If the entry defines a PCM buffer, it will define the compression type of the data to be received. The MT92210 can support TDM data in PCM A-law, PCM u-law, ADPCM-40, ADPCM-32, ADPCM-24 and ADPCM-16 formats. It can also perform auto-detection of the compression rate received using encoded values ...
Page 113
... TX Circular Buffer Base [20:8] / SOP [14:5] Write Offset [10:0] Add [6:0] 1’s Cnt b12 b11 b10 Circular Buffer Base [20:9] / Size Indication N Figure TDM Control Memory Zarlink Semiconductor Inc Buf Size History & Valid MT92210 113 ...
Page 114
... HT HDLC Type. ‘0’ = bit wise packet framing and escape code; ‘1’ = byte wise packet framing and escape code. 114 Description Table 40 - Fields and Description Zarlink Semiconductor Inc. ...
Page 115
... MT92210 : 115 ...
Page 116
... HDLC Address LUT Base [20:6] for HDLC Stream 0 HDLC Address LUT Base [20:6] for HDLC Stream 1 HDLC Address LUT Base [20:6] for HDLC Stream 510 HDLC Address LUT Base [20:6] for HDLC Stream 511 Zarlink Semiconductor Inc SOP [7:5] ...
Page 117
... TX Connection Structure Base [20:5] for Address = 0 TX Connection Structure Base [20:5] for Address = 1 TX Connection Structure Base [20:5] for Address = N-2 TX Connection Structure Base [20:5] for Address = N-1 Figure 63 - HDLC Address LUT (RTP) Table 42 - Fields and Description Zarlink Semiconductor Inc Description MT92210 117 ...
Page 118
... However, when the received data is ADPCM and silence suppression is being performed, the MT92210 is incapable of extracting the energy level of the silence from the ADPCM samples. Therefore, the magnitude of the original PCM value must be transmitted somehow to the MT92210. This is done on an associated stream single sample of an xxPCM channel now occupies 2 H.110 TSSTs. ...
Page 119
... MT92210 119 ...
Page 120
... Table 43 - Fields and Description b10 PCM Buffer Number [9:0] b10 HDLC Stream Number [8:0] b10 LLL Buffer Number [6:0] Figure 66 - Stream/Buffer Tag Format Zarlink Semiconductor Inc ...
Page 121
... H.110 streams (i.e. ct_d [0] and ct_d [1], during the same time slot). The even stream contains the data that is logically first. The format of the RX TDM Control Memory is the following: Description Table 44 - Fields and Description Zarlink Semiconductor Inc. MT92210 121 ...
Page 122
... RX Circular Buffer Base [20:8] / Size Indication RX Circular Buffer Write Pointer [15:0] RX Circular Buffer Read Pointer [15:0] b12 b11 b10 Circular Buffer Base [20:8] / Size Indication Figure TDM Control Memory Zarlink Semiconductor Inc Padding Type ...
Page 123
... Address at which the next byte to be sent out on the HDLC stream will be read from in Read Pointer the RX Circular Buffer. This field is written to the RX HDLC Stream/Buffer Control Entries each time it is modified. Description Table 45 - Fields and Description Zarlink Semiconductor Inc. MT92210 123 ...
Page 124
... RX Circ Buf Base [20:16] RX Circ Buf Base [20:16 Zarlink Semiconductor Inc ...
Page 125
... Packets in the HDLC Circular Buffers have already been zero inserted/byte inserted. Entry 0 Entry 1 Entry 510 Entry 511 b12 b11 b10 Circular Buffer Base [20:8] and Size Circular Buffer Write Pointer [15:0] Circular Buffer Read Pointer [15:0] Description Table 46 - Fields and Description Zarlink Semiconductor Inc MT92210 125 ...
Page 126
... RX TDM Data Formats When interfacing with external compression or silence suppression agents in xxPCM, the MT92210 uses special data formats that allow it to pass more than payload information over the H.110 bus. When transmitting ADPCM data, the position of the highest ‘1’ in the data sample indicates the type of compression used: in this way, all ADPCM compression types can be encoded within a single payload byte ...
Page 127
... MT92210 127 ...
Page 128
... Figure 72 - Format of RX xxPCM TSSTs - Zarlink Semiconductor Inc. Fields covered by CRC16 (PCM-R not included in CRC16) Explicit Underrun Indication (present until another CN/voice packet is received) ...
Page 129
... Ignore CN Packet. b13 b12 b11 b10 CN=0 Padding Type CN=2 Padding Type Figure Packet Conversion Lookup Table Description Table 47 - Fields and Description Zarlink Semiconductor Inc CN=1 Padding Type CN=3 Padding Type CN=253 Padding Type CN=255 Padding Type MT92210 129 ...
Page 130
... Zarlink Semiconductor Inc. ...
Page 131
... Bus Master Mode When acting as a bus master, the MT92210 can choose bus master on A, master on B, backup backup on B. When acting as a bus backup, the MT92210 uses the same error signals described above to determine if the current bus master is still valid should take over the bus. Note that the bus mastership can be overridden in registers by ensuring that the chip cannot drive the H ...
Page 132
... Figure 77 - TDM Bus Timing - Compatibility Clock Generation (other than sclk, sclkx2) 132 Figure 76 - TDM Bus Timing - sclkx2 Generation Zarlink Semiconductor Inc. : ...
Page 133
... As mentioned earlier, H.110 requires that the lower 16 streams on the bus be capable of running MHz, with a single clock frequency determined for each group of 4 streams. The MT92210 allows every group of 4 streams on the bus to operate MHz, allowing all 32 streams to be used in backwards compatibility with another non-H ...
Page 134
... Zarlink Semiconductor Inc. ...
Page 135
... The user need only generate upclk . The clock that is connected to the mem_clk_xxx inputs on the MT92210, whether it is TTL or PECL, must be in phase with the clock connected to SSRAM used with the chip. The maximum skew allowed is ± 0.5 ns. ...
Page 136
... Table 49 - Clock Divisor Z Clock Divisor CKOUT REF fc1pll FB Clock Divisor Clock Divisor CKOUT REF fc2pll FB Clock Divisor Figure 78 - Clock Synthesis Zarlink Semiconductor Inc. Clock Divisor mem_clk_sar_o fast_clk Clock Divisor mem_clk_net_o ...
Page 137
... Clock Recovery Since the MT92210 interfaces with a TDM bus necessary that it incorporate a clock recovery circuit that will allow it to generate a precise TDM clock. As such, the MT92210 contains data gathering hardware to accumulate information concerning timing VCs or channels, as well as clock generation mechanisms. ...
Page 138
... RTP Sequence Number Sequence number of the packet that caused this Adaptive Clock Recovery Event Structure to be written. RTP Timestamp Timestamp of the packet that caused this Adaptive Clock Recovery Event Structure to be written. 138 Description Table 50 - Fields and Description Zarlink Semiconductor Inc. ...
Page 139
... Programmable Fractional Divisor (Range = 2 to65535) Figure 81 - Adaptive Clock Recovery Modules Zarlink Semiconductor Inc. MT92210 E Written to clock recovery buffer in external memory bank A adapa_ref E Written to clock recovery buffer in ...
Page 140
... Pll_clk 140 Edges and Level Monitor Figure 82 - GPIO Functionality Zarlink Semiconductor Inc. gpio[7:0], ct_netref1, ct_netref2 Internal_pll_clk ...
Page 141
... Memory Controllers The MT92210 uses 3 separate memory banks, each with its own memory controller. Memory bank A is used for structures in the TX direction. Memory bank B is used for structures in the RX direction. Memory bank C is used by the device’s network interface. Each memory bank can connect external SSRAM chips, each ranging in size from 128K to 1M bytes ...
Page 142
... Zarlink Semiconductor Inc. ...
Page 143
... Data Sheet 12.0 Pin-out The following list describes the pin-out of the MT92210 device. Some pins have multiple functions, however, each pin bears the name of its principal function. All outputs are 3.3 V outputs only. Pins identified with in Type tolerate 5V for inputs and outputs. (F) All pins are tested with load, unless otherwise specified. ...
Page 144
... I/O Z Zarlink Semiconductor Inc. LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 8 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) Schmitt 12 mA (F) 200 pf load ...
Page 145
... Zarlink Semiconductor Inc. MT92210 PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load ...
Page 146
... X 18.75 37 18.75 37 18.75 37 18.75 37 18.75 37 Zarlink Semiconductor Inc. LVTTL (F) LVTTL (F) LVTTL LVTTL 4 mA (F) LVTTL LVTTL LVTTL (F) LVTTL 4 mA LVTTL 8 mA (F) LVTTL 8 mA LVTTL (F) LVTTL 4 mA LVTTL 4 mA LVTTL LVTTL LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 147
... I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z Zarlink Semiconductor Inc. MT92210 LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 148
... Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z Zarlink Semiconductor Inc. LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 149
... O 1 18.75 37 18.75 37 18.75 37 Zarlink Semiconductor Inc. MT92210 LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 150
... LVTTL 4 mA LVTTL 4 mA LVTTL 8 mA (F) LVTTL 4 mA (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a UTOPIA PHY Layer LVTTL (F) 1. MT92210 is a UTOPIA ATM Laye1. 2. MT92210 is a UTOPIA PHY Layer LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) ...
Page 151
... LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 8 mA (F) LVTTL 4 mA (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a UTOPIA PHY Layer LVTTL (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a UTOPIAPHY Layer LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) ...
Page 152
... PHY Layer 3. MT92210 is POS-PHY Link Layer LVTTL 8 mA (F) 1. MT92210 is UTOPIA ATM/PHY Layer 2. MT92210 is a POS-PHY Link Layer LVTTL (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a UTOPIA PHY Layer 3. MT92210 is a POS-PHY Link Layer LVTTL LVTTL LVTTL MT92210 is UTOPIA PHY ...
Page 153
... LVTTL (F) LVTTL (F) 1. MT92210 is UTOPIA ATM/PHY Layer 2. MT92210 is POS-PHY Link Layer LVTTL 8 mA (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a UTOPIA PHY Layer 3. MT92210 is a POS-PHY Link Layer LVTTL (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a UTOPIA PHY Layer 3 ...
Page 154
... Zarlink Semiconductor Inc. LVTTL 1. MT92210 is UTOPIA PHY Layer 2. MT92210 is POS-PHY Link Layer LVTTL (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) 0V Power Supply used for ...
Page 155
... Power C22 vss_ring Power C25 vss_ring Power C26 vss_ring Power D27 vss_ring Power E3 vss_ring Power E28 vss_ring Power F3 vss_ring Power F28 vss_ring Power J3 vss_ring Power J28 vss_ring Power K3 vss_ring Power K28 vss_ring Power N3 vss_ring Power Zarlink Semiconductor Inc. MT92210 155 ...
Page 156
... T17 vss_ring Power T18 vss_ring Power U3 vss_ring Power U13 vss_ring Power U14 vss_ring Power U15 vss_ring Power U16 vss_ring Power U17 vss_ring Power U18 vss_ring Power U28 vss_ring Power V3 vss_ring Power V13 vss_ring Power V14 vss_ring Power 156 Zarlink Semiconductor Inc. ...
Page 157
... Power F19 vdd33_ring Power F22 vdd33_ring Power F23 vdd33_ring Power G6 vdd33_ring Power H25 vdd33_ring Power J25 vdd33_ring Power K6 vdd33_ring Power L6 vdd33_ring Power M25 vdd33_ring Power N25 vdd33_ring Power P6 vdd33_ring Power Zarlink Semiconductor Inc. MT92210 3.3V Power Supply used for core and I/Os. 157 ...
Page 158
... AB25 vdd33_ring Power AC25 vdd33_ring Power F25 vdd33_ring Power G25 vdd33_ring Power K25 vdd33_ring Power L25 vdd33_ring Power P25 vdd33_ring Power R25 vdd33_ring Power V25 vdd33_ring Power W25 vdd33_ring Power F8 vdd33_ring Power F9 vdd33_ring Power F12 vdd33_ring Power 158 Zarlink Semiconductor Inc. ...
Page 159
... Additional 0V power supply pins. Additional 0V power supply pins. 5V Power Supply used for 5V tolerance. May be connected to 3.3Vpower supply if all devices connected to the MT92210 are 3.3V only. See vdd5_0. See vdd5_0. See vdd5_0. See vdd5_0. See vdd5_0. See vdd5_0. See vdd5_0. See vdd5_0. See vdd5_0. ...
Page 160
... E25 NC 160 Zarlink Semiconductor Inc. 0V PLL power supply. See Figure PLL noise reduction circuit for reference design. 2.5V PLL power supply. See Figure PLL noise reduction circuit for reference design. 2.5V Core power supply. See vdd25_0 See vdd25_0 See vdd25_0 ...
Page 161
... AG14 NC AH4 NC AH7 NC AH12 NC AJ4 NC AJ27 NC AJ28 NC AK28 NC vdd25 vdd25 vdd25 10 ohm 1/10W 5% 0.1uF 50V 10% 10 ohm 1/10W 5% 0.1uF 50V 10% 10 ohm 1/10W 5% 0.1uF 50V 10% Figure 84 - PLL Noise Reduction Circuits Zarlink Semiconductor Inc. MT92210 fc1pll_pllvdd fc1pll_pllvss fc2pll_pllvdd fc2pll_pllvss h110pll_pllvdd h110pll_pllvss 161 ...
Page 162
... Zarlink Semiconductor Inc. ...
Page 163
... TSTG - 150 TSTG - 125 VDD Overstress: 2x VDD (7.2 V) Symbol VDD + 2.25 to 2. 125 Condition _ 1023 RTP Connections, all output pins loaded _ Zarlink Semiconductor Inc. MT92210 Limits Unit °C ° Limits Unit V °C °C Min ...
Page 164
... VDD3.3- 0.5 LVTTL Comm/Ind 2.0 Temp Range 5-Volt Compatible 2.0 – – – – – 0.8 – 0 VDD or VSS - VDD VSS - 2 Zarlink Semiconductor Inc. Min Typ Max 1.7 – VDD V +0.3 – 1.35 2.0 V – 1.7 2.0 V 0.8 1.0 – V 0.6 0.7 – 200 390 uA -28 -185 ...
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... Yes 25 MHz 50 MHz No 25 MHz 50 MHz No 25 MHz 50 MHz No 25 MHz 50 MHz No 25 MHz 25 MHz No 25 MHz 25 MHz No 65.536 MHz No 8.192 MHz No Zarlink Semiconductor Inc. MT92210 Typ Max Unit 40% 60 40% 60% 400 ps 40% 60% 400 ps 40% 60% 400 ps 40% ...
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... Figure 85 - Non-multiplexed CPU Interface - Intel Mode 166 Write Access Read Access t1 t8 t13 t7 t4 *Access Active Generation inmo_cs write_access_active inmo_rd_ds Zarlink Semiconductor Inc read_access_active ...
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... Figure 86 - Non-multiplexed CPU Interface - Motorola Mode Write Access Read Access *Access Active Generation inmo_cs read_access_active inmo_rd_ds inmo_wr_rw Zarlink Semiconductor Inc. MT92210 t3 t3 t10 t11 t3 t3 t14 t12 t10 t11 inmo_cs write_access_active inmo_rd_ds inmo_wr_rw 167 ...
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... Figure 87 - Multiplexed CPU Interface - Intel Mode 168 Write Access t15 t1 t16 t17 Read Access t15 t1 t16 t17 t8 t13 t7 t4 *Access Active Generation inmo_cs write_access_active inmo_rd_ds Zarlink Semiconductor Inc read_access_active ...
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... Write Access t15 t1 t16 t17 Read Access t15 t1 t16 t17 t9 t8 t14 t7 *Access Active Generation inmo_cs read_access_active inmo_rd_ds inmo_wr_rw Min Typical Zarlink Semiconductor Inc. MT92210 t3 t3 t10 t11 t3 t3 t12 t10 t11 write_access_active Max Unit Notes 2 * upclkp - 4 ns 169 ...
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... Read Access Time (to external memory) t8 read_access_active falling edge to inmo_d driven 170 Min Typical upclkp 0 see Table 52 see Table upclkp - 4 Zarlink Semiconductor Inc. Max Unit Notes see Table upclkp ns see Table 52 ns see Table 52 ns ...
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... Note 2: MCLK_SAR = MCLK_NET = 82 MHz, and Upclk = 32.768 MHz Min Typical 0 0 1.5 0 upclkp - 4 upclkp - Max. 640 680 720 760 760 820 Table Write Access Time Zarlink Semiconductor Inc. MT92210 Max Unit Notes Test Unit Conditions ns Note 1 ns Note 2 ...
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... Table Read Access Time Zarlink Semiconductor Inc. Unit Test Conditions ns Note 1 ns Note 2 ns Note 1 ns Note 2 ns Note 1 ns Note 2 ns Note 1 ns Note 2 ns Note 1 ...
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... Zarlink Semiconductor Inc. Max. Unit Test Conditions 700 ns Note 1 760 ns Note 2 740 ns Note 1 920 ns Note 2 860 ns Note 1 960 ns Note 2 860 ns Note 1 960 ns Note 2 760 ns Note 1 820 ns Note 2 800 ns Note 1 840 ns Note 2 940 ns Note 1 1.04 us Note 2 940 ns Note 1 1.2 us Note MT92210 173 ...
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... H.110 Output t10 t10 t11 t11 ct_c8 ct_c8 ct_c8 H.110 Frame Sampling H.110 Frame Sampling t20 t21 t20 t21 ct_c8 ct_c8 ct_frame ct_frame Figure 90 - H.110 Input Output Zarlink Semiconductor Inc. Typ Max Units Test Conditions ...
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... H.110 Message Transmission Delay H.110 Message Transmission Delay H.110 Message Transmission Delay t40 t40 t40 t41 t41 t41 H.110 Message Reception Delay H.110 Message Reception Delay t50 t50 ct_mc ct_mc ct_mc mc_rx mc_rx mc_rx Figure 91 - H.110 Message Handling Zarlink Semiconductor Inc. MT92210 175 ...
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... Min 102 102 Table 54 - Fields and Description Zarlink Semiconductor Inc. Typical Max Unit 122 ...
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... Min 3 3 Table 54 - Fields and Description (continued Min Typical 3.1 0 1.1 1.9 Table 55 - Fields and Description Zarlink Semiconductor Inc. Typical Max Unit Max Unit MT92210 Notes 200 pf 200 pf Notes Load = 50 pf Load = 50 pf 177 ...
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... Because of this, the exponential section of the delay entries is located in the delay section in which early packet will arrive. In addition, the time_zero_delta field must be programmed to the total number of frames of latency with which the latest packet can be expected to arrive (from source to destination). Zarlink Semiconductor Inc. MT92210 179 ...
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... HDLC Format, Including Zero-Insertion and Extraction The MT92210 supports 2 types of HDLC over the TDM bus: the first, bit-wise form of HDLC uses a control flag of “01111110” and inserts a '0' after every 5 '1's of payload. When using this form of HDLC, each HDLC packet must begin with a flag and end with a flag, although a single flag may represent both the end of a packet and the beginning of another ...
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... Data Sheet Appendix C Standards & Specifications The MT92210 is designed to conform to sections of the following standards and specifications. Some of these specifications define requirements that can only be implemented in software. Some of the specifications are “umbrella” specifications to which the MT92210 only complies to portions of. ECTF H.100 Revision 1.0 Hardware Compatibility Specification: CT Bus H ...
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... Af-phy-0017.000: UTOPIA Specification Level 1, version 2.01 Af-phy-0039.000: UTOPIA Level 2, version 1.0 PMC-Sierra POS-PHY: Saturn Compatible Packet over SONET Interface Specification (Level 2) 184 Zarlink Semiconductor Inc. ...
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... HDLC (H igh-level D ata L ink C ontrol ): An encapsulation protocol that defines specific bit patterns as delimiters and thus allows transmission of data over a serial link. In the MT92210, HDLC is used to carry variable-length packets on the H.110 bus nternet P rotocol ): Designed for use in interconnected systems of packet-switched computer communication networks the ubiquitous protocol on which the Internet runs ...
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... VCI is a 16-bit number that is included in the header of an ATM cell. VPI (V irtual P ath I dentifier ): A virtual path determines the way an ATM cell should be routed. The VPI is an 8-bit (in UNI) or 12-bit (in NNI) number that is included in the header of an ATM cell. WATOMIC: An uninterruptable Write operation. 186 Zarlink Semiconductor Inc. ...
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... Null VC contains data in which some or all of the headers have been encoded into the VC number itself. For example, a Null-application data VC's payload would begin with the application data itself (either RTP or the payload) with UDP header, and no SNAP/LLC, LANE or other headers. Null encapsulation is referred to in IETF RFC2684 as VC Multiplexing. Zarlink Semiconductor Inc. MT92210 187 ...
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E/4 D/4 ISSUE ACN DATE APPRD. DIMENSION Conforms to JEDEC MS - 034 Rev. A NOTES: 1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994. 2. ALLDIMENSIONS ARE ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...