MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 121

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
When the RX Channel Association Memory points to an RX xxPCM Buffer Structure in the RX TDM Control
Memory, the entry contains a pointer to the RX circular buffer used. In addition, law translation can be done in the
RX direction: the data coming from the circular buffer can be u-law or A-law and it can exit on H.110 as u-law or
A-law. The RX xxPCM Buffer Structure contains a Padding Type field that indicates where padding data should
come from if no valid data is available in the circular buffer, in the case of underruns or packet loss. The Padding
Type field can be updated by the packet disassembly module: when a CN packet is received, a new Padding Type
value can be written in the circular buffer. When the RX TDM reads this value, it updates its Padding Type in the RX
TDM Control Memory, then uses that value to pad from then on.
The RX xxPCM Buffer Structure also contains an Invalid Byte Counter that counts, in ms, how long it has been
since a valid byte was received, with a maximum value of FFh (255 ms).
If the RX Channel Association Memory points to an HDLC Stream Buffer Structure in the RX TDM Control Memory,
the information contained in that structure indicates the base address and size of the RX Circular Buffer associated
to that HDLC stream, as well as the current read and write pointers to that circular buffer. If there is no data
contained in the circular buffer, then an idle code will be sent onto the H.110 bus (either 7Eh in byte-framing or FFh
in bit-framing). Otherwise, the next available byte in the circular buffer will be sent onto the bus. All HDLC framing
has already been done by the packet disassembly module.
The RX Channel Association Memory also has an AS (Associated Stream) bit that allows greater bandwidth on
HDLC streams; this bit is identical in function to the one in the TX direction. When this bit is ‘1’, the RX Channel
Association Memory binds 2 time slots to the corresponding RX TDM Control Memory entry instead of 1. This
increases the total capacity of the RX Data Path in HDLC mode to 2046 time slots. In this mode, the 2 time slots
that are bound together are 2 adjacent H.110 streams (i.e. ct_d [0] and ct_d [1], during the same time slot). The
even stream contains the data that is logically first.
The format of the RX TDM Control Memory is the following:
PCM Buffer
Number
HDLC Stream
Number
LLL Buffer
Number
Field
Points to 8-byte PCM entry in RX TDM Control Structure
Points to 16-byte HDLC entry in RX TDM Control Structure (must be aligned on a 16-byte
boundary)
Points to LLL 4-byte circular buffer
Table 44 - Fields and Description
Zarlink Semiconductor Inc.
Description
MT92210
121