TS83102G0B ATMEL Corporation, TS83102G0B Datasheet
TS83102G0B
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TS83102G0B Summary of contents
Page 1
... Standard Die Flow (upon Request) Description The TS83102G0B is a monolithic 10-bit analog-to-digital converter, designed for digi- tizing wide bandwidth analog signals at very high sampling rates Gsps. It uses an innovative architecture, including an on-chip Sample and Hold (S/H). The 3.3 GHz full power input bandwidth and band flatness performances enable the digitiz- ing of high IF and large bandwidth signals ...
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... The TS83102G0B works in a fully differential mode from analog inputs to digital outputs. A dif- ferential Data Ready output (DR/DRB) is available to indicate when the outputs are valid and an Asynchronous Data Ready Reset ensures that the first digitized data corresponds to the first acquisition ...
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... LVDS output compatibility PLUSD Maximum operating VPLUSD , D VEE , V IN INB 50 Ω differential or single-ended - V INB 50 Ω single-ended clock input or 100 Ω differential clock , P CLKB (recommended) TS83102G0B Comments Value GND to 6.0 GND to -5.7 GND - 1.1 to 2.5 GND to -5.5 0.3 -1.5 to 1.5 -1 GA, SDA - 0.8 PGEB, DECB V min operating -2 ...
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... Analog Inputs Full-scale input voltage range (differential mode common mode voltage) Full-scale input voltage range (single-ended input option common mode voltage) TS83102G0B 4 Comments Commercial "C" grade Industrial "V" grade common mode voltage and performances are guaranteed in the PLUSD range (from -0 ...
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... P CLK 4 V CLK V CLK 4 V CLKB 4 C CLK R CLK R CLK TS83102G0B common mode PLUSD range (from -0.9V to 1.7V); PLUSD Min Typ Max - 2 0 100 102 Differential ECL to LVDS -1 ±200 ±320 ±500 ±141 ±226 ± ...
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... Differential output buffers impedance = 100 Ω differential (50 Ω single-ended). See Figures starting on page 42. Notes: 2. Histogram testing Gsps, Fin = 100 MHz, DNLrms is a component of quantization noise. 3. Histogram testing Msps, Fin = 25 MHz 4. This range of gain can be set to "1" by using the gain adjust function. TS83102G0B 6 Test Level Symbol ...
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... Fin = 100 MHz Fs = 1.4 Gsps Fin = 700 MHz Fs = 1.4 Gsps Fin = 1950 MHz Gsps Fin = 2 GHz 2101C–BDC–02/04 Test Level Symbol 4 FPBW (1) 4 SSBW VSWR Max J 4 SINAD 4 ENOB 4 SNR TS83102G0B Max) J Min Typ Max 3.3 3.5 ± 0.2 ± 0.3 1.1 :1 1.2 7.5 8.0 7.0 7.6 6.8 7.1 6.1 6.5 ...
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... Notes: 1. See “Definition of Terms” on page 35. 2. From DC to 1.5 GHz 3. Specified from 2.5 GHz input signal. Input VSWR is measured on a soldered device. It assumes an external 50 Ω ±2 Ω controlled impedance line, and a 50 Ω driving source impedance (S TS83102G0B 8 J Test Level Symbol ...
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... Gsps Fin = 2 GHz 2101C–BDC–02/04 Min) C Test Level Symbol Min 41 4 SINAD 6.5 4 ENOB 6.3 6.2 6 SNR ITHDI ISFDRI TS83102G0B Typ Max Unit 6.8 6.7 Bit 6.4 6 dBC ...
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... TD1 = T/2 + (|TOD - TDR|) and TD2 = T/2 + (|TOD - TDR|), where T = clock period. This places the ris- ing edge (True/False) of the differential data ready signal in the middle of the output data valid window. This gives maximum setup and hold times for external data acquisition. TS83102G0B 10 Test ...
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... Unless otherwise specified 2. Refer to “Ordering Information” on page 55. Only minimum and maximum values are guaranteed (typical values are issued from characterization results). 2101C–BDC–02/04 (1) (2) (for "C" temperature range) (1) and sample tested at specified temperatures (for "V" temperature ranges TS83102G0B ( ...
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... Figure 2. Timing Diagram Regeneration Latches Note: TS83102G0B 12 N N+1 Analog input TA External clock Internal clock N N+1 Latch 1 N Latch 2 N Latch 3 Latch 4 Latch 5 Latch 6 Latch 7 Output Latches Latch 8 Data ready Pipeline Delay = 4 clock cycles Outputs Detailed timing diagrams are provided on page 39. N+2 N+1 N+2 N+1 N+2 N N+1 N+2 N N+1 N+2 Logic encoding ...
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... None 3 AlCu AlCu Oxyde nitride -5V TS83102G0B GRAY (B/ MSB………....LSB Out-of-Range ...
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... TS83102G0B Package Description Table 4. Pin Description (CBGA 152) Symbol Pin Number Power Supplies K1, K2, J3, K3, B6, C6, A7, B7, C7, P8, Q8 CCTH B1, C1, D1, G1, M1, Q1, B2, C2, D2, E2, F2, G2, N2, P2, Q2, A3, B3, D3, E3, F3, G3, N3, P4, GND Q4, R4, A5, P5, Q5, P6, Q6, P7, Q7, R7, B9, B10, B11, R11, P12, A14, B14, C14, G14, K14, ...
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... A9 DRRB SDA A6 SDAEN P1 2101C–BDC–02/04 TS83102G0B Function Decimation function enable or die junction temperature measurement: - Decimation active when connected to V junction temperature monitoring is not possible) - Normal mode when connected to Ground or left floating - Die junction temperature monitoring when current is applied Active low pattern generator enable ...
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... Figure 3. Pinout Notes: TS83102G0B 16 OR ORB DIODE TS83102G0BM DECB/ PGEB CI-CGA 152 BOTTOM VIEW 1. To simplify PCB routing, the 4 NC balls can be electrically connected to the GND balls. 2. The pinout is shown from the bottom. The columns and rows are defined differently from the JEDEC standard. 2101C– ...
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... C/W thermal grease resistance + 4.0° C/W RTH Example of the calculation of the ambient temperature T assuming RTH = 10.35° C/W and power dissipation = 4 110 - (10.35 x 4.6) = 62.39° air flow ( 2 m/s, for example). TS83102G0B is around 30° C/W. Therefore, to lower JA is typically 4.0° C/W (0 m/s air flow or CA is: JA max to ensure T A max = T A ...
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... To complete the thermal analysis, you must add the thermal resistance from the top of the board (on which the device is soldered) to the ambient resistance, whose values are user- dependent (the type of board, thermal, routing, area covered by copper in each board layer, thickness, airflow or cold plate are all parameters to consider). TS83102G0B ...
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... Figure 5. Full Power Input Bandwidth Typical VSWR Versus Figure 6. VSWR Curve for VIN and CLK Input Frequency 2101C–BDC–02/04 0.0 -0.5 -1.0 -1.5 Gain Flatness (±0.15 dB) -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 Fin (MHz) 1.7 1.6 1.5 1.4 1.3 CLK 1.2 1.1 1.0 0 500 1000 1500 TS83102G0B = 80°C; -1 dBFS, unless other Bandwidth VIN 2000 2500 3000 Frequency (MHz) 3500 19 ...
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... Typical Step Tr measured = sqrt (Tr Response Tr PulseGenerator Actual Tr Figure 7. Step Response (Random Interleaved Sampling Method Measure) Figure 8. Zoom on Rise Time Step Response Note: TS83102G0B 20 2 PulseGenerator = 41 ps (estimated ADC 1000 800 600 400 200 0 4.00E-15 2.00E-10 4.00E-10 800 700 600 ...
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... Frequency in Nyquist Conditions Sampling Frequency (Fin = Fs/2) Figure 10. SFDR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) Figure 11. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) Figure 12. SNR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) 2101C–BDC–02/04 TS83102G0B 400 600 ...
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... Performances Versus Frequency 1.4 Gsps Fin and Fs = 1.7 Gsps Figure 14. THD Versus Input Frequency 1.4 Gsps and Fs = 1.7 Gsps Figure 15. SFDR Versus Input Frequency 1.4 Gsps and Fs = 1.7 Gsps Figure 16. SNR Versus Input Frequency 1.4 Gsps and Fs = 1.7 Gsps TS83102G0B 1.4 Gsps 1.7 Gsps ...
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... The input frequency is chosen to respect the coherence of the acquisition. Figure 17 1.4 Gsps and Fin = 702 MHz, -1 dBFS; Decimation Factor = 16, 32 kpoints FFT Figure 18 1.4 Gsps and Fin = 1399 MHz, -1 dBFS; Decimation Factor = 16, 32 kpoints FFT 2101C–BDC–02/04 TS83102G0B 23 ...
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... Figure 19 1.7 Gsps and Fin = 898 MHz, -1 dBFS; Decimation Factor = 16, 32 kpoints FFT Figure 20 1.7 Gsps and Fin = 1699 MHz, -1 dBFS; Decimation Factor = 8, 32 kpoints FFT Figure 21 Gsps and Fin = 1998 MHz, -1 dBFS; Decimation Factor = 8, 32 kpoints FFT TS83102G0B 24 2101C–BDC–02/04 ...
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... MHz 10 MHz -64 dBFS -75 dBFS -60 -80 -100 -120 0 50 100 150 200 The output data is not decimated. The spectrum is displayed from DC to 600 MHz. TS83102G0B =205 MHz -7 dBFS 2F2 + F1 2F1 - 595 MHz 215 MHz 400 MHz -63 dBFS -65 dBFS -73 dBFS 250 300 ...
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... Figure 24. Dual Tone Reconstructed Signal Spectrum 1.4 Gsps, Fin1 = 745 MHz, Fin2 = 755 MHz (-7 dBFS), IMD3 = 65 dBFS Note: Figure 25. Dual Tone Reconstructed Signal Spectrum 1.4 Gsps, Fin1 = 995 MHz, Fin2 = 1005 MHz (-7 dBFS), IMD3 = 64 dBFS Note: TS83102G0B (Fs/8) + Fin1 = 45 MHz -10 -7 dBFS ...
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... The ADC input signal is sampled at 1.4 Gsps but data acquisition is 8 times decimated. Thus, the spectrum is displayed from DC to Fs/2 divided by the decimation factor [(Fs/2)/8 = 87.5 MHz]. The dual tone IMD3 at 1.4 Gsps is around -65 dBFS for Fin = 1 GHz ± 250 MHz (Fin range is from 750 MHz to 1250 MHz). TS83102G0B 2F2 + MHz -60 dBFS MHz ...
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... Typical Performance Sensitivity Versus Power Supply and Temperature Figure 27. ENOB Versus Junction Temperature (Fs = 1.4 Gsps, Fin = 698 MHz, -1 dBFS) Figure 28. SFDR Versus Junction Temperature (Fs = 1.4 Gsps, Fin = 698 MHz, -1 dBFS) Figure 29. SNR Versus Junction Temperature (Fs = 1.4 Gsps, Fin = 698 MHz, -1 dBFS) TS83102G0B 28 8 7.5 7 6 ...
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... I = 4.75V, 5V and 5.25V) EE 8.00 7.50 7.00 6.50 6.00 ±5 V and 4.75V, 5V and 5.25V) EE -40.00 -45.00 -50.00 -55.00 -60.00 -65.00 -70.00 ±5 V and 1.4 Gsps Versus Fin 4.75V, 5V and 5.25V) EE ±5 V TS83102G0B ; Fs = 1.4 Gsps Versus Fin Fin (MHz) ±5.25 V ±4. 1.4 Gsps Versus Fin Fin (MHz) ±5.25 V ±4.75 V Fin (MHz) ±5.25 V ±4. ...
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... SINAD = 47 dB • THD = -55.7 dB (over 25 harmonics) • SFDR = -62.6 dBc • SNR = 47.3 dB TS83102G0B 30 = 80°C; Bin Spacing = (Fs/2) / 16384 = 2.67 kHz J Fin = -8 x (fs/16) + 702 MHz = 2 MHz SFDR = -63 dBc The thermal noise floor is expressed in dBm/Hz ( 300 Hz): 10 log (kTB/1 mW) = -174 dBm/Hz or -139.75 dBm/2.67 kHz. THD is calculated over the 25 first harmonics ...
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... Therefore, the thermal noise can be extracted from the ENOB: the ENOB without a referred input thermal noise is 9.2 instead of 7.6 in this example, only limited by the quantization noise and clock induced jitter. 2101C–BDC–02/04 TS83102G0B 31 ...
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... Equivalent Input/Output Schematics Figure 34. Equivalent Analog Input Circuit and ESD Protections Note: Figure 35. Equivalent Clock Input Circuit and ESD Protections Note: TS83102G0B 32 VIN 50Ω controlled transmission line (bounding + package + ball) Package GND Die Pads Pins 50Ω controlled VINB transmission line (bounding + package + ball) 100 Ω ...
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... Figure 36. Equivalent Data Output Buffer Circuit and ESD Protections Figure 37. ADC Gain Adjust Equivalent Input Circuits and Protections 2101C–BDC–02/04 TS83102G0B 50 Ω 50 Ω 50 Ω 33 ...
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... Figure 38. B/GB and PGEB Equivalent Input Schematics and ESD Protections Figure 39. DRRB Equivalent Input Schematics and ESD Protections TS83102G0B 34 2101C–BDC–02/04 ...
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... Time to recover 0.2% accuracy at the output, after a 150% full-scale step applied on the input is reduced to midscale TS83102G0B Where A is the actual input amplitude and V is the full-scale range of the ADC under test 35 ...
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... Settling Time Voltage Standing VSWR Wave TS83102G0B 36 PSRR is the ratio of input offset variation to a change in power supply voltage The ratio expressed the RMS signal amplitude, set below full-scale, to the RMS value of the next highest spectral component (peak spurious spectral component). ...
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... TS83102G0B Operating Features Timing Information Timing Value for The timing values are defined in the “Electrical Operating Characteristics” on page 4. TS83102G0B The timing values are given at the package inputs/outputs, taking into account the package’s transmission line, bond wire, pad and ESD protections capacitance, as well as specified termi- nation loads. The evaluation board propagation delays in 50 Ω ...
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... Data Ready signal (DR/DRB) [zero crossing point]. Note: TS83102G0B 38 For normal initialization of the Data Ready output signal, the external encoding clock signal fre- quency and level must be controlled. The minimum encoding clock sampling rate for the ADC is 150 Msps, due to the internal Sample and Hold drop rate ...
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... Timing Diagram Figure 40. TS83102G0B Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at LOW Level INB CLK/CLKB TOD = 360 ps Digital Outputs TDR = 410 ps Data Ready DR/DRB Data Ready Reset Figure 41. TS83102G0B Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at HIGH Level ...
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... In the differential mode input configuration, this means 0.25V on each input, or ±125 mV around 0V. The input common mode is ground. Figure 43. Differential Inputs Voltage Span (Full-scale) The TS83102G0B analog input features a 100 Ω (±2%) differential input impedance Dynamic Issues Ω // 0.3 pF). Each analog input (VIN,VINB) is terminated by 50 Ω single-ended (100 Ω ...
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... Clock Inputs (CLK/CLKB) The TS83102G0B clock inputs are designed for either single-ended or differential operation. The device’s clock inputs are on-chip 100 Ω Ω) differentially terminated. The termina- tion mid point is AC coupled to ground through on-chip capacitor. Therefore, either ground or different common modes can be used (ECL, LVDS) ...
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... Moreover, proper active signal shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs. The analog and clock inputs of the TS83102G0B device have been surrounded by ground pins, which must be directly connected to the external ground plane. ...
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... PLUSD VPLUSD = - 0.8V 50 Ω Ω Ω 50 Ω 10.5 mA VPLUSD = -0. Ω 50 Ω Ω 10.5 mA TS83102G0B should be supplied with -0.8V (or PLUSD should be tied to 1.45V PLUSD can be set to ground. VOL typ = -1.17V OUT VOH typ = -0.94V OUTB Differential Output Swing: ±0.23V = 0.46 Vpp 50 Ω ...
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... VPLUSD = 1.45V 50 Ω LVDS Logic Figure 50. LVDS Format (Refer to the IEEE Standards 1596.3 - 1994): 1125 mV < Common Compatibility Mode <1275 mV and 250 mV < Output Swing < 400 mV Common Mode Each Single-ended Output TS83102G0B 44 50 Ω Ω Ω 50 Ω 10.5 mA Zc=50 Ω 50 Ω ...
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... Gsps). A standard technique for reducing the ampli- tude of such errors down to ±1 LSB consists in setting the digital output data to gray code format. However, the TS83102G0B has been designed to feature a Bit Error Rate of 10-12 with a binary output format. ...
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... Figure 51. Recommended Diode Pin Implementation Allowing for Both Die Junction Temper- ature Monitoring Function and Decimation Mode Figure 52. Diode Pin Implementation for Decimation Activation TS83102G0B 46 The ADC decimation test mode is different from the pattern generator function, which is used to check the ADC’s outputs. ...
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... TS83102G0B IGND Idiode A10 Vdiode V VGND DXP Temperature Sensor DXN Jonction Temperature (°C) 1mA = 1 mA) ...
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... This feature is particularly interesting for interleaving ADCs to increase the sampling rate. The variation of the delay around its nominal value as a function of the SDA voltage is shown in Figure 57 (simulation result). Figure 57. Typical Tuning Range (±120 ps for Applied Control Voltage Varying Between -0.5V and 0.5V on the SDA Pin) 400 p 300 p 200 p 100 p -500 m -400 m TS83102G0B 48 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 ...
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... GND 50 ohm microstrip lines CLKb CLK DRRB CAL1 Differential clock inputs 37. 50. 6. 78.00 mm TS83102G0B ADC 10 bits 2 Gsps Packaged pins connector 2.54 mm pitch Evaluation Board General Design Without Drivers GND GND GND GND banana VDD GND VEET GND B/GB ...
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... Applying the TS83102G0B with the TS81102G0 Demultiplexer The TS83102G0B output data rate can be demultiplexed times by using the TS81102G0 (8/10-bit parallel channel 2 Gsps 1:4/1:8 demultiplexer). The ADC’s evaluation of static and dynamic performances can be done using the TSEV83102G0BGL ADC evaluation board, coupled with the TS81102G0 DMUX evaluation board and an acquisition system ...
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... Ceramic body size : Ball pitch : 1.27 mm Cofired : Al2O3 Optional: discrete capacitor mounting lands on the top side of the package for extra decoupling. 2101C–BDC–02/04 Metalic Cap 9.27 x 9.27 mm 21.00 mm ± 0. 152 0.80 ± (Position of array of columns/ref A and B) 0.15 T (Position of balls within array) TS83102G0B 51 ...
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... Figure 61. Isometric View Figure 62. Package Top View TS83102G0B 52 21. 4.335 2.50 mm Marking Area 2 6.815 mm CuW 7 brazed on 9 metallization 4.335 mm These lands are designed for discrete capacitor device 0603 size (1.6 x 0.8 mm) 2.50 mm 9.270 mm Marking Area 1 CuW is connected Pin A1 Index (0.50 mm Full Circle) 2101C– ...
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... For additional decoupling of power supplies, extra land capacitors can be used, as shown in Fig- ures . They are not required if following the evaluation board’s decoupling recommendations or if using standard power supply sources (performance results of the device have proven to be equivalent without these capacitors). TS83102G0B 4.335 mm 2.50 mm Capacitor discrete devices are 0603 size (1 ...
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... Figure 64. Cross Section TS83102G0B 54 CBGA 152 21x21 mm Cross Section 10 bits/2 Gsps ADC. External heatsink required Al2O3 ceramic CuW Heat Spreader brazed on Al2O3 at VEE=-5 Volt potential Location for external heatsink 1.25 +/- 0.12 mm 0.65 mm 0.50 +/- 0.05 mm Low T˚ Solder balls Diam 0. 1.27 mm grid Combo Lid soldered 9. ...
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... T <90° “V” -20°C < <110° Ambient Die Ambient TS83102G0B Screening Level Comments Standard product Standard product Evaluation Board Prototype (delivered with a heat sink) UPON REQUEST ONLY Visual inspection (please contact your local Atmel sales office) 55 ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...