TS83102G0B ATMEL Corporation, TS83102G0B Datasheet - Page 2

• Manufacturer Part Number: TS83102G0B
• Description: 10-bit 2 GSPS ADCthis State-of-the-art 10-bit 2 GSPS Converter Offers an Unprecedented Bandwidth of 3.3 GHZ And Excellent Band Flatness, Allowing to Directly Digitize Very High if Signals (2nd And 3rd Nyquist Zones) With High Linearity : The SFDR Rem
• Manufacturer: ATMEL Corporation

Functional Description
2
TS83102G0B
Figure 1. Simplified Block Diagram
The TS83102G0B is a 10-bit 2 Gsps ADC. The device includes a front-end master/slave Track
and Hold stage (Sample and Hold), followed by an analog encoding stage (Analog Quantizer),
which outputs analog residues resulting from analog quantization. Successive banks of
latches regenerate the analog residues into logical levels before entering an error correction
circuit and resynchronization stage, followed by 50 Ω differential output buffers.
The TS83102G0B works in a fully differential mode from analog inputs to digital outputs. A dif-
ferential Data Ready output (DR/DRB) is available to indicate when the outputs are valid and
an Asynchronous Data Ready Reset ensures that the first digitized data corresponds to the
first acquisition.
The control pin B/GB (A11 of the CBGA package) is provided to select either a binary or gray
data output format. The gain control pin GA (R9 of the CBGA package) is provided to adjust
the ADC gain transfer function.
A Sampling Delay Adjust function (SDA) may be used to ease the interleaving of ADCs.
A pattern generator is integrated on the chip for debug or acquisition setup. This function is
activated through the PGEB pin (A9 of the CBGA package).
An Out-of-range bit (OR/ORB) indicates when the input overrides 0.5 Vpp.
A selectable decimation by 32 functions is also available for enhanced testability coverage
(A10 of the CBGA package), along with the die junction temperature monitoring function.
The TS83102G0B uses only vertical isolated NPN transistors together with oxide isolated pol-
ysilicon resistors, which allows enhanced radiation tolerance (over 100 kRad (Si) total dose
expected tolerance).
CLKB
VINB
CLK
VIN
GA
50
50
50
50
SDA
SDA
Sample &Hold
Clock generation
PGEB
Logic block
DIODE
DECB/
B/GB
DRRB
2101C–BDC–02/04
OR
ORB
D9
D9B
D0
D0B
DR
DRB