TS83102G0B ATMEL Corporation, TS83102G0B Datasheet - Page 41

• Manufacturer Part Number: TS83102G0B
• Description: 10-bit 2 GSPS ADCthis State-of-the-art 10-bit 2 GSPS Converter Offers an Unprecedented Bandwidth of 3.3 GHZ And Excellent Band Flatness, Allowing to Directly Digitize Very High if Signals (2nd And 3rd Nyquist Zones) With High Linearity : The SFDR Rem
• Manufacturer: ATMEL Corporation

Clock Inputs (CLK/CLKB)
Differential Clock
Inputs Voltage Levels
(0 dBm Typical)
2101C–BDC–02/04
The TS83102G0B clock inputs are designed for either single-ended or differential operation.
The device’s clock inputs are on-chip 100 Ω (2 x 50 Ω) differentially terminated. The termina-
tion mid point is AC coupled to ground through a 40 pF on-chip capacitor. Therefore, either
ground or different common modes can be used (ECL, LVDS).
Note:
However, logic ECL or LVDS square wave clock generators are not recommended because of
poor jitter performances. Furthermore, the propagation times of the biasing tees used to offset
the common mode voltage to ECL or LVDS levels may not match. A very low-phase noise
(low jitter) sinewave input signal should be used for enhanced SNR performance, when digitiz-
ing high frequency analog inputs. Typically, when using a sinewave oscillator featuring a
-135 dBc/Hz phase noise, at 20 KHz from the carrier, a global jitter value (including the ADC
and the generator) of less than 200 fs RMS has been measured. If the clock signal frequency
is at fixed rates, it is recommended to narrow-band filter the signal to improve jitter
performance.
Note:
A single to differential balun with sqrt (2) ratio may be used (featuring a 50 Ω input impedance
with 100 Ω differential termination).
For instance:
The recommended clock input’s common mode is ground.
Figure 44. Differential Clock Inputs - Ground Common Mode (Recommended)
4 dBm is equivalent to 1 Vpp into 50 Ω and 1.4 Vpp into 100 Ω termination (secondary).
0 dBm is equivalent to 0.632 Vpp into 50 Ω and 0.632 x sqrt (2) = 0.894 Vpp into 100 Ω ter-
mination (secondary), ± 0.226V at each clock input.
As long as V
than the 1V peak, it is necessary to AC couple the signal via 100 pF capacitors, for example,
and to bias CLK and CLKB:
- CLK biased to ground via a 10 kΩ resistor
- CLKB biased to ground via a 10 kΩ resistor and to V
The clock input buffer’s 100 Ω termination load is on-chip and mid-point AC coupled (40 pF) to
the chip’s ground plane, whereas the analog input buffer’s 100 Ω termination is soldered inside
the package cavity and mid-point DC coupled to the package ground plane.Therefore, driving
the analog input in single-ended mode does not perturb the chip’s ground plane (since the ter-
mination mid-point is connected to the package ground plane). However, driving the clock input
in single-ended mode does perturb the chip’s ground plane (since the termination mid-point is
AC coupled to the chip’s ground plane). Therefore, it is required to drive the clock input in differ-
ential mode for minimum chip ground plane perturbation (a 4 dBm maximum operation is
recommended). The typical clock input power is 0 dBm. The minimum operating clock input
power is -4 dBm (equivalent to a 250 mV minimum swing amplitude), to avoid SNR performance
degradations linked to the clock signal’s slew rate.
+0.23
-0.23
IH
remains below the 1V peak, the ADC clock can be DC coupled. If V
V
CLK
EE
via a 100 kΩ resistor.
CLKB
TS83102G0B
0V
t
IH
is higher
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