PIC18LF8720 Microchip Technology, PIC18LF8720 Datasheet - Page 273

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PIC18LF8720

Manufacturer Part Number
PIC18LF8720
Description
(PIC18LF6620/6520/8520/6620/8620/6720/8720) 64/80-Pin High-Performance / 64-Kbyte Enhanced Flash Microcontrollers
Manufacturer
Microchip Technology
Datasheet

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BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PC
No
Q1
PIC18F6520/8520/6620/8620/6720/8720
Read literal
operation
Unconditional Branch
[ label ] BRA
-1024
(PC) + 2 + 2n
None
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
1
2
HERE
1101
No
Q2
‘n’
=
=
address (HERE)
address (Jump)
n
0nnn
BRA
1023
operation
Process
Data
No
Q3
n
PC
Jump
nnnn
Write to PC
operation
No
Q4
nnnn
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Bit Set f
[ label ] BSF
0
0
a
1
None
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value.
1
1
BSF
Read
1000
Q2
=
=
f
b
[0,1]
f<b>
255
7
0x0A
0x8A
FLAG_REG, 7, 1
bbba
Process
Data
Q3
f,b[,a]
DS39609B-page 271
ffff
register ‘f’
Write
Q4
ffff

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