PIC18LF8720 Microchip Technology, PIC18LF8720 Datasheet - Page 75

• Manufacturer Part Number: PIC18LF8720
• Description: (PIC18LF6620/6520/8520/6620/8620/6720/8720) 64/80-Pin High-Performance / 64-Kbyte Enhanced Flash Microcontrollers
• Manufacturer: Microchip Technology

6.2
The External Memory Interface implemented in
PIC18F8X20 devices operates only in 16-bit mode.
The mode selection is not software configurable, but is
programmed via the configuration bits.
The WM<1:0> bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A<15:0> are
available on the External Memory Interface bus.
Following the address latch, the Output Enable signal
(OE) will enable both bytes of program memory at once
to form a 16-bit instruction word. The Chip Enable
signal (CE) is active at any time that the microcontroller
accesses external memory, whether reading or writing;
it is inactive (asserted high) whenever the device is in
Sleep mode.
FIGURE 6-1:
 2004 Microchip Technology Inc.
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
PIC18F8X20
16-bit Mode
AD<15:8>
A<19:16>
AD<7:0>
PIC18F6520/8520/6620/8620/6720/8720
WRH
WRL
ALE
CE
OE
16-BIT BYTE WRITE MODE EXAMPLE
373
373
D<7:0>
A<19:0>
D<15:8>
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
6.2.1
Figure 6-1 shows an example of 16-bit Byte Write
mode for PIC18F8X20 devices. This mode is used for
two separate 8-bit memories connected for 16-bit oper-
ation. This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
16-BIT BYTE WRITE MODE
A<x:0>
D<7:0>
CE
OE
(MSB)
WR
(1)
Address Bus
Data Bus
Control Lines
D<7:0>
DS39609B-page 73
A<x:0>
D<7:0>
CE
OE
(LSB)
WR
(1)