MT58L256L36D Micron Semiconductor, MT58L256L36D Datasheet
MT58L256L36D
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MT58L256L36D Summary of contents
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... DD Cycle Deselect ) MARKING -6 -7.5 -10 MT58L512L18D MT58L256L32D MT58L256L36D NOTE: 1. JEDEC-standard MS-026 BHA (LQFP GENERAL DESCRIPTION The Micron speed, low-power CMOS designs that are fabricated us- None ing an advanced CMOS process. IT Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced syn- chronous peripheral circuitry and a 2-bit burst counter ...
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ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 18 ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# ...
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GENERAL DESCRIPTION (continued) Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also ...
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TQFP PIN ASSIGNMENT TABLE PIN # x18 x32/x36 PIN # 1 NC NF/DQPc DQc DQc DQc DQc 32 33 ...
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ADV# 83 ADSP# 84 ADSC# 85 ...
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ADV# 83 ADSP# 84 ADSC# 85 ...
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TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32-35, 44-50, 32-35, 44-50, 80-82, 99, 81, 82, 99, 100 100 92 (T Version Version Version Version BWa BWb# – ...
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TQFP PIN DESCRIPTIONS (CONTINUED) x18 x32/x36 SYMBOL 84 84 ADSP ADSC MODE (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72 12, (b) 68, 69 13, 18, ...
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CE# BWb# NC CE2# BWE CE2 NC BWa# CLK GW ...
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FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11P, 10P, 10R, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 9A 9A ADV ADSP ADSC MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 3C, 3D, 3E, 3C, 3D, 3E, V 3F, 3G, 3J, 3F, 3G, 3J, 3K, 3L, 3M, 3K, 3L, 3M, 3N, 9C, 9D, 3N, 9C, 9D, 9E, 9F, 9G, 9E, 9F, 9G, 9J, 9K, ...
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INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 PARTIAL TRUTH TABLE FOR ...
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TRUTH TABLE OPERATION Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD ........................................................................... Relative to V -0.5V to +4.6V Voltage Supply DD ........................................................................... Relative to V -0.5V to +4.6V V (DQx) ............................................ -0. (inputs) ............................................ -0.5V to ...
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FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods 1-layer (Junction to Ambient) and procedures for measuring thermal Thermal Resistance (Junction to Top of Case) FBGA ...
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I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (0°C T 70° +3.3V +0.3V/-0.165V unless otherwise noted DESCRIPTION CONDITIONS Power Supply Device selected; All inputs Current Cycle time IH Operating V ...
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C T 70° DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid ...
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TEST CONDITIONS Input pulse levels .................. V .................... V Input rise and fall times ..................................... 1ns Input timing reference levels ...................... V Output reference levels ............................ V Output load ............................. See Figures 1 and 2 LOAD DERATING CURVES Micron 512K ...
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SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS GW#, BWE#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# (NOTE 3) t KQLZ Q ...
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KC CLK ADSS t ADSH ADSP# t ADSS ADSC ADDRESS A1 Byte write signals are ignored for first cycle when ADSP# initiates burst. BWE#, BWa#-BWd# GW# t CES t CEH ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# (NOTE 4) t CES t CEH CE# (NOTE 2) ADV# OE High-Z t KQLZ Q ...
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PIN #1 ID 14.00 ±0.10 +0.20 16.00 -0.05 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, ...
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BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 5.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. ...
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REVISION HISTORY Removed "Preliminary Package Data" from front page ......................................................................... February 22/02 Removed 119-pin PBGA package and references .................................................................................. February 14/02 Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................. June 7/01 Added industrial temperature references and notes, Rev. ...