MT9045 Zarlink Semiconductor, MT9045 Datasheet
MT9045
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MT9045 Summary of contents
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... France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1/OC3 System Synchronizer MT9045AN 48 pin SSOP • Provides Time Interval Error (TIE) correction • Accepts reference inputs from two independent sources • ...
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... The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference. ...
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... RST Reset (Input). A logic low at this input resets the MT9045. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. The RST pin should be held low to a minimum of 300ns. While the RST pin is low, all frame pulses except RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high ...
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... Internal Connection. Tie low for normal operation. 43 PRIOOR Primary Reference Out Of Capture Range (Output). A logic high at this pin indicates that the Primary reference is off the nominal frequency by more than MT9045 Description The logic level at this input is gated in by the rising edge of 4 Zarlink Semiconductor Inc ...
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... Reference Select MUX Circuit The MT9045 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1 and Table 4 ...
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... This results in a phase alignment between the input reference signal and the output signal as shown in Figure 14. The speed of the phase alignment correction is limited to 5ns per 125us, and convergence is in the direction of least phase travel. The state diagram of Figure 7 indicates which state changes the TIE Corrector Circuit is activated. MT9045 TCLR Resets Delay Control ...
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... Digital Phase Lock Loop (DPLL) As shown in Figure 4, the DPLL of the MT9045 consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit. Virtual Reference Phase from Detector TIE Corrector Feedback Signal from Frequency Select MUX Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two ...
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... Normal Mode. See Figures 14 & 16. All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g., 30pF) loads. MT9045 T1 Divider C1.5o 12MHz ...
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... When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the MT9045 is based on the incoming signal 30ms minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e ...
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... FS2 and FS1 as shown in Table 1. Fast Lock Mode Fast Lock Mode is a submode of Normal Mode used to allow the MT9045 to lock to a reference more quickly than Normal Mode will allow. Typically, the PLL will lock to the incoming reference within 500ms if the FLOCK pin is set high ...
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... Intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. In the MT9045, the intrinsic Jitter is limited to less than 0.02UI on the 2.048MHz and 1.544MHz clocks. ...
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... Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT9045, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. Holdover Accuracy Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques ...
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... PRIOOR and SECOOR pins will be +/-21.6ppm. If there are no clock transitions at the Primary and Secondary reference inputs when the MT9045 is configured to operate with 8kHz or 19.44MHz, then the PRIOOR and SECOOR pins will provide a 50ns high pulse width occurring once every 1 ...
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... For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9045 loop filter and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently, phase lock time, which is not a standards requirement, may be longer than in other applications ...
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... Refer to Control State Diagram for state changes to and from Auto-Holdover State S1 {A} Normal Auto-Holdover Primary (000) (PCCi=0) (PCCi=1) NOTES: (XXX) MS2 MS1 RSEL {A} Invalid Reference Signal Movement to Normal State from any state requires a valid input signal MT9045 Normal Normal Freerun (PRI) (SEC MTIE MTIE S2 S2 MTIE ...
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... Another consideration in determining the accuracy of the master timing source is the desired capture range. The sum of the accuracy of the master timing source and the capture range of the MT9045 will always equal 230ppm. For example, if the master timing source is 100ppm, then the capture range will be 130ppm. ...
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... Rise & Fall Time:10ns (0.33V 2.97V 15pF) Duty Cycle: 40% to 60% The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9045, and the OSCo output should be left open as shown in Figure 8. Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made crystal, resistor and capacitors is shown in Figure 9 ...
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... MT9045 from Normal Mode to Holdover Mode • 200ns is the maximum phase continuity of the MT9045 from Holdover Mode to Normal Mode (with or without TIE Corrector Circuit) When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case holdover was entered for 2s, each mode change sequence could still account for a phase change as large as 350ns ...
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... Capacitor’s discharge time Resistor value (3.3 MΩ Capacitor value (1µ Negative going threshold voltage of the T- Schmitt Trigger (2 3 MT9045 MT9045 +3.3V R 10kΩ RST R P 1kΩ C 10nF Figure 10 - Power-Up Reset Circuit 19 Zarlink Semiconductor Inc. Data Sheet ...
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... A digital alternative to the RC-time-constant circuit is presented in Figure 12. The circuit in Figure 12 can be used to generate a steady lock signal. The circuit monitors the MT9045’s LOCK pin, as long as it detects a positive pulse every 1.024 seconds or less, the Advanced Lock output will remain high positive pulse is detected on the LOCK output within 1 ...
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... OSCi = Clock 3 CMOS high-level input voltage 4 CMOS low-level input voltage 5 Input leakage current 6 High-level output voltage 7 Low-level output voltage * Supply voltage and operating temperature are as per Recommended Operating Conditions. MT9045 Voltages are with respect to ground (V ) unless otherwise stated. SS Symbol PIN I PIN T ...
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... Rise and Fall Threshold Voltage High 3 Rise and Fall Threshold Voltage Low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case result of the CMOS thresholds. * See Figure 12. MT9045 Sym ±0ppm ±32ppm ±100ppm ± 0ppm ± ...
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... AC Electrical Characteristics - Input/Output Timing PRI/SEC 8kHz PRI/SEC 1.544MHz PRI/SEC 2.048MHz PRI/SEC 19.44MHz F8o NOTES: 1. Input to output delay values are valid after a TCLR or RST with no further state changes Figure 14 - Input to Output Timing (Normal Mode) MT9045 Timing Reference Points R15D R2D R19D ...
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... C19o pulse width high 28 C19o pulse width low 29 F0o pulse width low 30 F8o pulse width high 31 F16o pulse width low 32 Output clock and frame pulse rise or fall time 33 Input Controls Setup Time 34 Input Controls Hold Time MT9045 Sym IRF t R8D t R15D t R2D t R19D t ...
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... F8o F0o F16o t C16WL C16o t t C8W C8W C8o t C4W C4o C2o t C6W C6o C1.5o t C19W C19o F8o C2o RSP TSP MT9045 t F0WL t F16WL t F16S t C4W t C2W t C6W t C15W t C19W Figure 15 - Output Timing 1 t RSPD t t TSPW RSPW t TSPD Figure 16 - Output Timing 2 25 Zarlink Semiconductor Inc ...
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... AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered Characteristics 1 Intrinsic jitter (4Hz to 100kHz filter) 2 Intrinsic jitter (10Hz to 40kHz filter) 3 Intrinsic jitter (8kHz to 40kHz filter) 4 Intrinsic jitter (10Hz to 8kHz filter) † See "Notes" following AC Electrical Characteristics tables. MT9045 Sym Max 0.0002 0.0002 0.0002 0.030 ...
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... Jitter attenuation for 10Hz@0.10UIpp input 4 Jitter attenuation for 60Hz@0.10UIpp input 5 Jitter attenuation for 300Hz@0.10UIpp input 6 Jitter attenuation for 3600Hz@0.005UIpp input † See "Notes" following AC Electrical Characteristics tables. MT9045 Sym Min Max Units 0.015 UIpp 0.010 UIpp 0.010 UIpp 0 ...
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... Jitter attenuation for 10Hz@20UIpp input 4 Jitter attenuation for 60Hz@20UIpp input 5 Jitter attenuation for 300Hz@20UIpp input 6 Jitter attenuation for 10kHz@0.3UIpp input 7 Jitter attenuation for 100kHz@0.3UIpp input † See "Notes" following AC Electrical Characteristics tables. MT9045 Sym Min Max Units ...
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... Jitter at output for 2400Hz@1.50UIpp input with 40Hz to 100kHz filter 12 13 Jitter at output for 100kHz@0.20UIpp input with 40Hz to 100kHz filter 14 † See "Notes" following AC Electrical Characteristics tables. MT9045 Sym Min Max Units 2.9 UIpp 0.09 UIpp 1.3 UIpp ...
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... Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz input 6 Jitter tolerance for 700Hz input 7 Jitter tolerance for 2400Hz input 8 Jitter tolerance for 10kHz input 9 Jitter tolerance for 100kHz input † See "Notes" following AC Electrical Characteristics tables. MT9045 Sym Min Max Units 0.80 UIpp 1-3,6,10 -15,22-23,25-27,29 0.70 UIpp 1-3,6,10 -15,22-23,25-27,29 0.60 ...
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... For Freerun Mode of 32ppm. ± 18. For Freerun Mode of 100ppm. ± 19. For capture range of 230ppm. ± 20. For capture range of 198ppm. ± 21. For capture range of 130ppm. 22. 25pF capacitive load. MT9045 Sym Min Max 150 140 130 Sym Min -0 -32 ...
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... No filter. 38. 40Hz to 100kHz bandpass filter. 39. With respect to reference input signal frequency. 40. After a RST or TCLR. 41. Master clock duty cycle 40% to 60%. 42. Prior to Holdover Mode, device was in Normal Mode and phase locked. MT9045 32 Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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