MT9045 Zarlink Semiconductor, MT9045 Datasheet - Page 5

• Manufacturer Part Number: MT9045
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Functional Description
The MT9045 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
Reference Select MUX Circuit
The MT9045 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1
and Table 4.
Frequency Select MUX Circuit
The MT9045 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or
19.44MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at
the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST)
must be performed after every frequency select input change. See Table 1.
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or
SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.
During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary
reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL
would lead to unacceptable phase changes in the output signal.
Pin Description (continued)
Pin #
44
45
46
47
48
Name
TRST
TDO
TMS
TCK
TDI
Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. If not used, this pin should be held low.
Test Clock (Input): Provides the clock to the JTAG test logic. This pin is internally pulled up to
V
Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to V
DD
.
0
1
FS2
0
1
Table 1 - Input Frequency Selection
FS1
0
1
0
1
Zarlink Semiconductor Inc.
MT9045
DD
5
.
Input Frequency
Description
19.44MHz
1.544MHz
2.048MHz
DD
8kHz
.
Data Sheet