MT9045 Zarlink Semiconductor, MT9045 Datasheet - Page 9

• Manufacturer Part Number: MT9045
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover)
when the frequency of the incoming signal is outside the Auto-Holdover capture range. (See AC Electrical
Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the
incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output
signal locked to the input signal. The holdover output signal in the MT9045 is based on the incoming signal 30ms
minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible
because the Holdover Mode is very accurate (e.g.,
and output after switching back to Normal Mode is preserved.
State Machine Control
As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the
DPLL. Control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). When
switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and
disabled when PCCi = 0.
All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation
section for full details.
Master Clock
The MT9045 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Control and Mode of Operation
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2.
Figure 6 - Control State Machine Block Diagram
RSEL
RSEL
0
1
Table 2 - Input Reference Selection
Select MUX
Reference
To
Zarlink Semiconductor Inc.
MS1
State Machine
±
MT9045
Corrector
0.05ppm).
To TIE
Enable
Control
Input Reference
9
MS2
SEC
PRI
To DPLL
Select
State
Consequently, the phase delay between the input
PCCi
Data Sheet