SL1935D ETC, SL1935D Datasheet - Page 4

• Manufacturer Part Number: SL1935D
• Description: Single Chip Synthesized Zero IF Tuner
• Manufacturer: ETC

SL1935
Quadrature Downconverter Section - continued
The oscillators share a common varactor line drive and
both require an external varactor tuned resonator
optimised for low phase noise performance. The
recommended application circuit for the local oscillators
is detailed in Fig.9 and the typical phase noise
performance is detailed in Fig.10. The local oscillator
frequency is coupled internally to the PLL frequency
synthesiser programmable divider input.
The mixer outputs are coupled to the baseband buffer
amplifiers, providing for one of two selectable baseband
outputs in each channel. The required output is selected
by bit BS in the I
outputs are fed off chip via ports ‘OPIA’ and ‘OPIB’
(‘OPQA’ and ‘OPQB’), then back on chip through ports
‘IPIA’ and ‘IPIB’ (‘IPQA’ and ‘IPQB’), allowing for the
insertion of two independent user definable filter
bandwidths. Each output provides a low impedance
drive (Fig.11) and each input provides a high impedance
load . An example filter for 30MS/s is detailed in Fig.13.
Both path gains are nominally equal. NB 6dB insertion
loss is assumed in each channel, however a different pot
down ratio may be applied.
Each baseband path is then multiplexed to the final
baseband amplifier stage, providing further gain and a
low impedance output drive. The nominal output load
test condition is detailed in Fig.14.
PLL Frequency Synthesiser Section
The PLL frequency synthesiser section contains all the
elements necessary, with the exception of a reference
frequency source and a loop filter to control the selected
oscillator to produce a complete PLL frequency
synthesised source. The device, produced using high
speed logic, allows for operation with a high comparison
frequency and enables the generation of a loop with
excellent phase noise performance.
The LO signal from the selected oscillator drives from the
phase splitter into an internal preamplifier, providing gain
and reverse isolation from the divider signals. The output
of the preamplifier interfaces directly with the 15-bit fully
programmable divider. The programmable divider has
MN+A architecture, the dual modulus prescaler is 16/17,
the A counter is 4-bits and the M counter is 11-bits.
The output of the programmable divider is fed to the
phase comparator and compared in both phase and
frequency domains to the comparison frequency. This
frequency is derived from either the on board crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider,
programmable into 1 of 29 ratios and detailed in Table 3.
The typical application for the crystal oscillator is shown
in Fig.15.
4
2
C bus transmission (Table 6). These
The output of the phase detector feeds a charge pump
and a loop amplifier. When used with an external loop
filter and a high voltage transistor it integrates the current
pulses into the varactor line voltage used to control the
selected oscillator.
The programmable divider output Fpd divided by two
and the reference divider output Fcomp are switched to
port P0 by programming the device into test mode. Test
modes are detailed in Table 4.
The crystal reference frequency can be switched to the
BUFREF output by bit RE as detailed in Table 7.
Programming
The SL1935 is controlled by an I
compatible with both standard and fast mode formats.
Data and Clock are fed on the SDA and SCL lines
respectively as defined by the I
device can either accept data (write mode) or send data
(read mode). The LSB of the address byte (R/W) sets the
device into write mode if it is low and read mode if it is
high. Tables 9a and 9b detail the format of the data. The
SL1935 may be programmed to respond to several
addresses and enables the use of more than one device
in an I
address is selected by applying a voltage to the ‘ADD’
input. When the device receives a valid address byte, it
pulls the SDA line low during the acknowledge period
and during following acknowledge periods after further
data bytes are received. When the device is
programmed into read mode, the controller accepting
the data must pull the SDA line low during all status byte
acknowledge periods to read another status byte. If the
controller fails to pull the SDA line low during this period,
the device generates an internal ‘STOP’ condition which
inhibits further reading.
Write mode
Bytes 2 and 3 contain frequency information bits 2
inclusive (Table 9). Byte 4 controls the synthesiser
reference divider ratio (Table 3) and the charge pump
setting (Table 5). Byte 5 controls test modes (Table 4),
baseband filter path select BS (Table 6), local oscillator
select VS (Table 8), buffered crystal reference output
select RE (Table 7) and the output port P0.
After reception and acknowledgment of a correct
address (byte 1), the first bit of the following byte
determines whether the byte is interpreted as byte 2 or
4, a logic ‘0’ indicates byte 2 and a logic ‘1’ indicates byte
4. Having interpreted this byte as either byte 2 or 4, the
following byte will be interpreted as byte 3 or 5
respectively. After receiving two complete data bytes,
additional data bytes may be entered and byte
interpretation follows the same procedure without re-
addressing the device. The procedure continues until a
‘STOP’ condition is received.
2
C bus system. Table 9c details the how the
2
2
C bus format. The
C data bus and is
14
to 2
0