SL1935D ETC, SL1935D Datasheet - Page 5

• Manufacturer Part Number: SL1935D
• Description: Single Chip Synthesized Zero IF Tuner
• Manufacturer: ETC

The STOP condition can be generated after any data
byte, if however it occurs during a byte transmission, the
previous byte data is retained. To facilitate smooth fine
tuning, the frequency data bytes are only accepted by
the device after all 15 bits of frequency data have been
received, or after the generation of a STOP condition.
Read mode
When the device is in read mode, the status byte read
from the device takes the form shown in Table 9b.
The typical key performance data at Vcc = 5V and +25 o C ambient are detailed in Table 1.
Table 2. Programmable Features
Synthesiser programmable divider
Reference programmable divider
Baseband filter path select
Local oscillator select
Charge pump current
Test mode
General purpose port, P0
Buffered crystal reference output,
BUFREF
Programmable features
Table 3. Reference division ratios
R4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R3
Function as described above
Function as described above.
Function as described above.
Function as described above.
The charge pump current can be programmed by bits C1 & C0 (Table 5).
The test modes are defined by bits T2 - T0 as described in Table 4.
The general purpose port can be programmed by bit P0;
The buffered crystal reference frequency can be switched to the BUFREF
output by bit RE as described in Table 7. The BUFREF output defaults to
the ‘ON’ condition at device power up.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Logic ‘1’ = on
Logic ‘0’ = off (high impedance)
R2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the Vccd supply to the device has dropped
below 3V (at 25 o C), e.g. when the device is initially turned
ON. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates that the programmed information may
have been corrupted and the device reset to the power
up condition.
Bit 2 (FL) indicates whether the synthesiser is phase
locked, a logic ‘1’ is present if the device is locked, and
a logic ‘0’ if the device is unlocked.
R0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Illegal state
Illegal state
Illegal state
Ratio
128
256
160
320
192
384
112
224
448
16
32
64
10
20
40
80
12
24
48
96
14
28
56
2
4
8
5
6
7
SL1935
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