ATSAM2133B ATMEL Corporation, ATSAM2133B Datasheet - Page 17

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ATSAM2133B

Manufacturer Part Number
ATSAM2133B
Description
Low-power Synthesizer
Manufacturer
ATMEL Corporation
Datasheet
Reset and Power-
down
2694A–DRMSD–05/03
www.DataSheet4U.com
During power-up, the RESET input should be held low until the crystal oscillator and
PLL are stabilized. This can take about 20 ms.
After the low-to-high transition of RESET, the following occurs:
If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power
switch is used, then the chip enters a deep power-down sleep mode, as power is
removed from the core. To exit power down, PDWN must be asserted high, then
RESET applied.
Power-down mode is managed by an internal power switch. The equivalent schematic
and standard connection is shown on the diagram below.
All the VC2 pins must be connected to PWROUT.
Figure 10. Schematic
Note:
Figure 11. PDWN Connection
Synthesis/DSP enters an idle state
P16 program execution starts from address 0100H in ROM space (WCS low)
High level for PDWN is VC2 = 2.5V ±10%.
VC2 Source from
HOST
Power Supply
VC3
3.3V
ATSAM2133B
(High level = 3.3V)
Control
PDWN
PDWN = L: Power-down Mode (Internal Power Switch Open)
PDWN = H: Operating Mode (Internal Power Switch Closed)
VC2
VC2
VC2
VC2
VC2
VC2
10 kOhm
PDWN
ATSAM2133B
VC3
3.3V
PWRIN
2.5V
ATSAM2133B
PWROUT
VC2
17

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