ATSAM2133B ATMEL Corporation, ATSAM2133B Datasheet - Page 5

• Manufacturer Part Number: ATSAM2133B
• Description: Low-power Synthesizer
• Manufacturer: ATMEL Corporation

Pin Description
100-lead TQFP Package
Table 1. Pin by Function - 100-lead TQFP Package
2694A–DRMSD–05/03
Pin Name
GND
VC2
VC3
PWRIN
PWROUT
D0 - D7
CS
WR
RD
A0
IRQ
RESET
X1, X2
CKOUT
DABD0 -1
CLBD
WSBD
DAAD
P0 - P3
DBCLK
DBDATA
DBACK
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Pin Number
10, 16, 31, 36,
45, 56, 68, 76,
80, 84, 96
11, 37, 83, 86,
87
17, 30, 44, 57,
69, 97
77
78
6-9, 12-15
2
4
3
5
1
22
81, 82
88
93, 92
94
95
98
18 - 21
90
91
89
TSOUT
Type
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
I/O
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
-
Function
Power ground - all GND pins should be returned to digital ground.
Core power +2.5V ±10%. All V
switch is used for minimum power down consumption, then all these pins should be
connected to PWROUT, the output of the built-in power switch.
Periphery power +2.25V to 3.7V. All V
should not be lower than V
Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin
must be connected to nominal 2.5V.
Power switch output. Use this pin to supply 2.5V core power by connecting it to all V
8-bit data bus to host processor. Information on these pins is parallel MIDI (MPU-401 type
applications)
Chip select from host, active low.
Write from host, active low.
Read from host, active low.
Selects MPU-401 internal registers:
0 = data registers (read/write)
1 = status register (read) control register (write)
Tri-state output pin, active high.
Master reset input, active low.
Crystal connection. Crystal frequency should be Fs*256 (typ 11.2896 MHz). Crystal
frequency is internally multiplied by 4 to provide the IC master clock. An external 11.2896
MHz clock can also be used on X1 (2.5V
used to drive external ICs; use CKOUT instead.
Buffered X2 output, can be used to drive external DAC master clock (256 * Fs)
Two stereo serial audio data output (4 audio channels). Each output holds 64 bits (2 x 32)
of serial data per frame. Audio data has up to 20 bits precision. DABD0 can hold additional
control data (mute, A/D gain, D/A gain, etc.)
Audio data bit clock, provides timing to DABD0 - 1, DAAD.
Audio data word select. The timing of WSBD can be selected to be I
compatible.
Stereo serial audio data input.
General-purpose programmable I/O pins.
Debug clock. Should be connected to V
just after RESET, then the internal ROM debugger/flash programmer is started.
Debug data. Allows serial communication for debug/flash programming.
Debug acknowledge. Toggled each time a bit is received/sent on DBDATA.
C2
.
C2
pins should be returned to +2.5V. If the built-in power
C3
C3
pins should be returned to nominal +3.3V. V
PP
under normal operation. If DBCLK is found low
max through 47pF capacitor). X2 cannot be
ATSAM2133B
2
S or Japanese
C2
C3
pins.
5