ATSAM2133B ATMEL Corporation, ATSAM2133B Datasheet - Page 18

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ATSAM2133B

Manufacturer Part Number
ATSAM2133B
Description
Low-power Synthesizer
Manufacturer
ATMEL Corporation
Datasheet
Recommended Board
Layout
18
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ATSAM2133B
Like all HCMOS high integration ICs, the following simple rules of board layout are man-
datory for reliable operation:
All GND, VC3, VC2 pins should be connected. A GND plane is strongly recommended
below the ATSAM2133B. The board GND + VC3 distribution should be in grid form.
Recommended VC2 decoupling is 0.1 µF at each corner of the IC with an additional 10
µF decoupling close to the crystal. VC3 requires a single 0.1uF decoupling.
The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-
R and the ATSAM2133B should be short and shielded. The ground return from the com-
pensation capacitors and LFT filter should be the GND plane from ATSAM2133B.
Parallel layout between D0 - D7 and WA0 - WA21/WD0 - WD15 should be avoided. The
D0 - D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses
on WA0 - WA21/WD0 - WD15 that can corrupt address and/or data on these buses.
A ground plane should be implemented below the D0 - D7 bus, which is connected to
the host and to the ATSAM2133B GND.
A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus,
which is connected to the ROM/Flash grounds and to the ATSAM2133B.
A specific AGND ground plane should be provided, which is connected to the GND
ground by a single trace. No digital signals should cross the AGND plane.
Refer to the Codec vendor recommended layout for correct implementation of the ana-
log section.
GND, VC3, VC2 Distribution and Decouplings
Crystal, LFT
Buses
Analog Section
2694A–DRMSD–05/03

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